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| ADVANCE INFORMATION MICRONAS MAS 3587F MPEG Layer 3 Audio Encoder/Decoder Edition March 2, 2001 6251-542-1AI MICRONAS MAS 3587F Contents Page 5 5 6 7 7 7 7 7 8 8 9 9 9 9 9 9 9 10 10 10 10 11 11 11 11 11 13 13 14 14 14 14 14 14 14 15 15 15 15 16 16 16 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.6. 2.7. 2.7.1. 2.7.1.1. 2.7.2. 2.7.2.1. 2.7.2.2. 2.7.3. 2.7.4. 2.8. 2.8.1. 2.8.2. 2.9. 2.9.1. 2.9.2. 2.9.3. 2.10. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.11.5. 2.11.6. 2.12. 2.13. 2.13.1. 2.13.2. 2.13.3. 2.13.4. 2.13.5. Title Introduction Features Application Overview ADVANCE INFORMATION Functional Description of the MAS 3587F Overview Architecture of the MAS 3587F DSP Core RAM and Registers Firmware and Software Internal Program ROM and Firmware, MPEG-Encoding/Decoding Program Download Feature Audio Codec A/D Converter and Microphone Amplifier Baseband Processing Bass, Treble, and Loudness Micronas Dynamic Bass (MDB) Automatic Volume Control (AVC) Balance and Volume D/A Converters Output Amplifiers Clock Management DSP Clock Clock Output at CLKO Power Supply Concept Power Supply Regions DC/DC Converters Power Supply Configurations Battery Voltage Supervision Interfaces I2C Control Interface S/PDIF Input Interface S/PDIF Output Multiline Serial Audio Input (SDI, SDIB) Multiline Serial Output (SDO) Parallel Input/Output Interface (PIO) MPEG Synchronization Output Default Operation Stand-by Functions Power-Up of the DC/DC Converters and Reset Control of the Signal Processing Start-up of the Audio Codec Power-Down 2 Micronas ADVANCE INFORMATION MAS 3587F Contents, continued Page 17 17 17 17 18 19 19 19 24 24 25 25 26 26 27 27 28 28 29 29 29 30 30 31 31 32 32 32 32 40 41 42 42 42 43 49 50 50 50 53 53 53 53 53 53 53 Section 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.2. 3.2.1. 3.2.2. 3.3. 3.3.1. 3.3.1.1. 3.3.1.2. 3.3.1.3. 3.3.1.4. 3.3.1.5. 3.3.1.6. 3.3.1.7. 3.3.1.8. 3.3.1.9. 3.3.1.10. 3.3.1.11. 3.3.1.12. 3.3.1.13. 3.3.1.14. 3.3.1.15. 3.3.2. 3.3.3. 3.3.3.1. 3.3.3.2. 3.3.4. 3.3.5. 3.4. 3.4.1. 3.4.2. 3.4.3. 3.4.4. 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. Title I2C Interface General Device Address I2C Registers and Subaddresses Naming Convention Direct Configuration Registers Write Direct Configuration Registers Read Direct Configuration Register DSP Core Access Protocol Run and Freeze Read Register (Code Ahex) Write Register (Code Bhex) Read D0 Memory (Code Chex) Short Read D0 Memory (Code C4hex) Read D1 Memory (Code Dhex) Short Read D1 Memory (Code D4hex) Write D0 Memory (Code Ehex) Short Write D0 Memory (Code E4hex) Write D1 Memory (Code Fhex) Short Write D1 Memory (Code F4hex) Clear SYNC Signal (Code 5hex) Default Read Fast Program Download Serial Program Download List of DSP Registers List of DSP Memory Cells Application Select and Running Application Specific Control Ancillary Data DSP Volume Control Audio Codec Access Protocol Write Codec Register Read Codec Register Codec Registers Basic MDB Configuration Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Reference Pins DC/DC Converters and Battery Voltage Supervision Oscillator Pins and Clocking Control Lines Parallel Interface Lines Micronas 3 MAS 3587F Contents, continued Page 54 54 54 54 54 54 54 54 55 55 56 58 58 59 62 63 64 66 68 69 70 71 72 76 77 79 80 82 Section 4.3.6.1. 4.3.7. 4.3.8. 4.3.9. 4.3.10. 4.3.11. 4.3.12. 4.3.13. 4.3.14. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.4. 4.6.5. 4.6.6. 4.7. 4.8. 5. Title PIO Handshake Lines Serial Input Interface (SDI) Serial Input Interface B (SDIB) Serial Output Interface (SDO) S/PDIF Input Interface S/PDIF Output Interface Analog Input Interfaces Analog Output Interfaces Miscellaneous Pin Configurations Internal Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Digital Characteristics I2C Characteristics Serial (I2S) Input Interface Characteristics (SDI, SDIB) Serial Output Interface Characteristics (SDO) S/PDIF Input Characteristics S/PDIF Output Characteristics PIO as Parallel Input Interface: DMA Mode PIO as Parallel Output Interface: DMA Mode Analog Characteristics DC/DC Converter Characteristics Typical Performance Characteristics Typical Application in a Portable Player Recommended DC/DC Converter Application Circuit Data Sheet History ADVANCE INFORMATION 4 Micronas ADVANCE INFORMATION MAS 3587F 1.1. Features Firmware - MPEG 1/2 layer 3 encoder MPEG Layer 3 Audio Encoder/Decoder This data sheet applies to MAS 3587F version A1. 1. Introduction The MAS 3587F is a single-chip MPEG layer 3 audio encoder/decoder designed for use in memory-based recording/playback applications, e.g. MP3 record/playback equipment. The IC contains a DSP engine with embedded RAM and ROM. It provides flexible digital interfaces for serial and S/PDIF audio data input and output. Also integrated are power management functions and two DC/DC converters for single cell power supply. A high-quality stereo D/A converter and a stereo A/D converter on chip provide the analog functions required in an advanced portable audio player. In encoding mode, audio data is input via the integrated A/D converter, serial PCM, or S/PDIF interface. The compressed digital data stream is sent via the parallel interface. In decoding mode, compressed digital data streams are accepted in the parallel or serial format. The audio data is output via the high quality D/A converter. A digital output in serial PCM format and/or S/PDIF format is also provided. Thus, the MAS 3587F provides a true 'ALL-IN-ONE' solution that is ideally suited for highly optimized memory based music recorders. Additional functionality is achieved via download software (e.g. Micronas SC4 encoder/decoder). SC4 is a proprietary Micronas speech codec technology based on ADPCM. The codec can be downloaded to the MAS 3587F to allow high quality speech recording and playing back at various sampling rates. (Please contact your local Micronas Sales Representative about availability of SC4 downloads). In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have been standardized. The most sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo signals while still maintaining CD audio quality. - Encoding with adaptive bit rate up to max. 192 kbit/s - MPEG 1/2 layer 2 and layer 3 decoder - Decoder-Extension to MPEG 2 layer 3 for low bit rates ("MPEG 2.5") - Extraction of MPEG Ancillary Data - Adaptive bit rates (bit rate switching) - SDMI-compliant security technology for decoder - Stereo channel mixer - Bass, treble and loudness function - Micronas Dynamic Bass (MDB) - Automatic Volume Control (AVC) Interfaces - 2 serial asynchronous interfaces for bitstreams and uncompressed digital audio - Parallel handshake bit stream input/output - Serial audio output via I2S and related formats - S/PDIF audio input - S/PDIF audio output - Controlling via I2C interface Hardware Features - Two independent embedded DC/DC converters (e.g. for DSP and flash RAM supply) - Low DC/DC converter start-up voltage (0.9 V) - DC converter efficiency up to 95 % - Battery voltage monitor - Low supply voltage (down to 2.2 V for decoder, 3.5 V for encoder) - Low power dissipation (<70 mW for decoder, <400 mW for encoder) - Hardware power management and power-off functions - Microphone amplifier - Stereo A/D converter for FM/AM-radio and speech input - CD quality stereo D/A converter - Headphone amplifier - On-chip crystal oscillator - External clock or crystal frequency of 13...20 MHz - Standby current < 10 A Micronas 5 MAS 3587F 1.2. Application Overview The following block diagram shows an example application for the MAS 3587F in a portable audio recorder device. Besides a simple controller and the external flash memories, all required components are integrated in the MAS 3587F. By means of the embedded A/D-Converter, the MAS 3587F supports both speech and FM radio quality audio encoding. CD-quality encoding/decoding is achieved by using digital inputs/ embedded D/A-Converter. ADVANCE INFORMATION Fig. 1-1 depicts a portable audio application that is power optimized. The two embedded DC/DC converters of the MAS 3587F generate optimum power supply voltages for the DSP core and also for state-of-the art flash memories that typically require 2.7 to 3.3 V supply. The performance of the DC/DC converters reaches efficiencies up to 95%. 3RUWDEOH 'LJLWDO 0XVLF 5HFRUGHU 0$6 ) line in Audio baseband features '63 &RUH Microphone amplifier MP3 encoding/ decoding Optional Software Downloads Headphone amplifier Volume Headphone A/D D/A optional digital in S/PDIF or serial digital out S/PDIF or serial Crystal Osc./PLL I2C DC/DC1 DC/DC2 Parallel I/O Bus System clock I2C Control e.g. 2.7 V e.g. 3.5 V / 2.2 V I2C Display Keyboard C PC Connector Fig. 1-1: Example application for the MAS 3587F in a portable audio recorder device 6 Flash RAM Micronas ADVANCE INFORMATION MAS 3587F 2.3. DSP Core The internal processor is a dedicated DSP for advanced audio applications. 2. Functional Description of the MAS 3587F 2.1. Overview The MAS 3587F is intended for use in consumer audio applications. It encodes analog audio input, PCM data or S/PDIF signals to variable bit rate MPEG 1/2 Layer 3 data streams. The compressed data is stored in an external memory via the parallel port. For playback it receives S/PDIF, parallel or serial data streams and decodes MPEG Layer 2 and 3 (including the low sampling frequency extensions). 2.4. RAM and Registers The DSP core has access to two RAM banks denoted D0 and D1. All RAM addresses can be accessed in a 20-bit or a 16-bit mode via I2C bus. For fast access of internal DSP states the processor core has an address space of 256 data registers which can be accessed by I2C bus. For more details please refer to Section 3.3. on page 24. 2.2. Architecture of the MAS 3587F The hardware of the MAS 3587F consists of a highperformance RISC Digital Signal Processor (DSP), and appropriate interfaces. A hardware overview of the IC is shown in Fig. 2-1. Mic. Input (incl. Bias) 1 Line Input 2 $XGLR &RGHF 2 A/D MIX Audio Proc. D/A 2 Audio Output '63 &RUH S/PDIF Input 1 S/PDIF Input 2 Serial Audio (I S, SDI) 2 ALU MAC Serial Audio (I2S, SDO) Accumulators ROM Output Select Input Select S/PDIF Output Control DCCF DCFR DSP Codec Serial Audio (stream, SDIB) VBAT Volt. Mon. D0 D1 I2C Interface I2C control V1 DC/DC 2 DC/DC 1 Registers Div. Div. V2 Parallel I/O Bus (PIO) Xtal 18.432 MHz Osc. PLL Synth. Synthesizer Clock Scaler /2 CLKO Fig. 2-1: The MAS 3587F architecture Micronas 7 MAS 3587F 2.5. Firmware and Software 2.5.1. Internal Program ROM and Firmware, MPEG-Encoding/Decoding The firmware implemented in the program ROM of the MAS 3587F provides MPEG 1/2 Layer 3 encoding and decoding of MPEG 1/2 Layer 2 and MPEG 1/2 Layer 3. The DSP operating system starts the firmware in the "Application Selection Mode". By setting the appropriate bit in the Application Select memory cell (see Table 3-6 on page 33), the MPEG audio encoder or decoder can be activated. ADVANCE INFORMATION The MPEG decoder provides an automatic standard detection mode. If all MPEG audio decoders are selected, the Layer 2 or Layer 3 bitstream is recognized and decoded automatically. For general control purposes, the operation system provides a set of I2C instructions that give access to internal DSP registers and memory areas. An auxiliary digital volume control and mixer matrix is applied to the digital stereo audio data. This matrix is capable of performing the balance control and a simple kind of stereo basewidth enhancement. All four factors LL, LR, RL, and RR are adjustable, please refer to Fig. 3-3 on page 41. S/PDIF S/PDIF2 Encoder SDI PIO S/PDIF SDO Audio Proc. LINE IN MIC IN A/D MIX D/A OUT Fig. 2-2: Encoder Signal Flow PIO Decoder SDIB DSP Volume Matrix S/PDIF SDO LINE IN MIC IN A/D MIX Audio Proc. D/A OUT Fig. 2-3: Decoder Signal Flow 8 Micronas ADVANCE INFORMATION MAS 3587F 2.7.1.1. Bass, Treble, and Loudness Standard baseband functions such as bass, treble, and loudness are provided (refer to Table 3-12 on page 43 for details). 2.5.2. Program Download Feature The standard functions of the MAS 3587F can be extended or substituted by downloading up to 4kWords (1 Word = 20 bits) of program code and additionally up to 4kWords of coefficients into the internal RAM. The code must be downloaded by the Fast Program Download command (see Section 3.3.1.14. on page 31) into an area of RAM that is switchable from data memory to program memory. A Run command (see Section 3.3.1.1. on page 25) starts the operation. 2.7.2. Micronas Dynamic Bass (MDB) The Micronas Dynamic Bass system (MDB) was developed to extend the frequency range of loudspeakers or headphones below the cutoff frequency of the speakers. In addition to dynamically amplifying the low frequency bass signals, the MDB exploits the psychoacoustic phenomenon of the `missing fundamental'. Adding harmonics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental, while at the same time retaining the loudness of the original signal. Due to the parametric implementation of the MDB, it can be customized to create different bass effects and adapted to various loudspeaker characteristics (see Section 3.4.4. on page 49). 2.6. Audio Codec A sophisticated set of audio converters and sound features has been implemented to comply with various kinds of operating environments that range up to highend equipment (see Fig. 2-4). Mic-In Mic-Amplifier incl. Bias Deemphasis 50s / 75s Line-In A D D Q-peak DSP A Mono 2.7.2.1. Automatic Volume Control (AVC) In a collection of tracks from different sources fairly often the average volume level varies. Especially in a noisy listening environment the user must adjust the volume to achieve a comfortable listening enjoyment. The Automatic Volume Correction (AVC) solves this problem by equalizing the volume level. To prevent clipping, the AVC's gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see Table 3-12 on page 43). For input levels of -18 dBr to 0 dBr, the AVC maintains a fixed output level of -9 dBr. Fig. 2-5 shows the AVC output level versus its input level. For volume and baseband registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. Mixer Mono/Stereo Q-peak AVC Bass/Treble Headphone Amplifier Audio Codec D A D A Volume Balance Loudness MDB Right invert Output Fig. 2-4: Signal flow block diagram of Audio Codec output level dBr -9 -15 -21 2.7. A/D Converter and Microphone Amplifier A pair of A/D converters is provided for recording or loop-through purposes. In addition, a microphone amplifier including voltage supply function for an electret type microphone has been integrated. ON OFF 2.7.1. Baseband Processing -30 -24 -18 -12 -6 0 +6 input level dBr The several baseband functions are applied to the digital audio signal immediately before D/A conversion. Fig. 2-5: Simplified AVC characteristics Micronas 9 MAS 3587F 2.7.2.2. Balance and Volume To minimize quantization noise, the main volume control is automatically split into a digital and an analog part. The volume range is -114...+12 dB with an additional mute position. A balance function is provided (see Table 3-12 on page 43). 2.8. Clock Management ADVANCE INFORMATION The MAS 3587F is driven by a single crystal-controlled clock with a frequency of 18.432 MHz. It is possible to drive the MAS 3587F with other reference clocks. In this case, the nominal crystal frequency must be written into memory location D0:7f3. The crystal clock acts as a reference for the embedded synthesizer that generates the internal clock. For compressed audio data reception, the MAS 3587F may act either as the clock master (Demand Mode) or as a slave (Broadcast Mode) as defined by bit 1 in IOControlMain memory cell (see Table 3-7 on page 34). In both modes, the output of the clock synthesizer depends on the sample rate of the decoded data stream as shown in Table 2-1. In the BROADCAST MODE (PLL on), the incoming audio data controls the clock synthesizer via a PLL. In the DEMAND MODE (PLL off) the MAS 3587F acts as the system master clock, the internal clock. The data transfer is triggered by a demand signal at pin EOD. This mode is used in most applications. In the encoder application, the MAS 3587F is clock master in case of I2S audio input. For S/PDIF input, the MAS 3587F synchronizes the clock to the incomming S/PDIF signal. Table 2-1: Settings of bits 8 and 17 in OutClkConfig and resulting CLKO output frequencies 2.7.3. D/A Converters A pair of Micronas' unique multibit sigma-delta D/A converters is used to convert the audio data with high linearity and a superior S/N. In order to attenuate highfrequency noise caused by noise-shaping, internal low-pass filters are included. They require additional external capacitors between pins FILTR and OUTR, and FILTL and OUTL respectively (see Section 4.7. on page 79). 2.7.4. Output Amplifiers The integrated output amplifiers are capable of driving stereo headphones of 16...32 impedance via 22- series resistors or built-in loudspeakers of 16 impedance directly. If more output power is required, the right output signal can be inverted and a single loudspeaker can be connected as a bridge between pins OUTL and OUTR. In this case the minimum impedance is 32 W, and for optimized power the source should be set to mono. MASF DAC DAC Output Frequency at CLKO/MHz OUTL OUTR R 32 Synth. Scaler On Scaler Plus Clock bit 8=0, bit 17=0 Extra Division fs/kHz bit 8=1 bit 8=0, bit 17=1 48 Fig. 2-6: Bridge operation mode 44.1 32 24.576 24 22.05 16 24.576 12 11.025 22.5792 8 24.576 512fs 768fs 6.144 5.6448 6.144 256fs 384fs 3.072 2.8224 3.072 22.5792 512fs 768fs 12.288 11.2896 12.288 256fs 384fs 6.144 5.6448 6.144 22.5792 24.576 512fs 768fs 24.576 22.5792 24.576 256fs 384fs 12.288 11.2896 12.288 10 Micronas ADVANCE INFORMATION MAS 3587F 2.9.2. DC/DC Converters The MAS 3587F has two embedded high-performance step-up DC/DC converters with synchronous rectifiers to supply both the DSP core itself and external circuitry such as a controller or flash memory at two different voltage levels. An overview is given in Fig. 2-7 on page 12. The DC/DC converters are designed to generate an output voltage between 2.0 V and 3.5 V which can be programmed separately for each converter via the I2C interface (see Table 3-3 on page 20). Both converters are of the bootstrapped type which allow start up from a voltage down to 0.9 V for use with a single battery or NiCd/NiMH cell. The default output voltages are 3.0 V. Both converters are enabled with a high level at pin DCEN and enabled/disabled by the I2C interface. The MAS 3587F DC/DC converters feature a constantfrequency, low noise pulse width modulation (PWM) mode and a low quiescent current, pulse frequency modulation (PFM) mode for improved efficiencies at low current loads. Both modes - PWM or PFM - can be selected independently for each converter via I2C interface. The default mode is PWM. In the PWM mode, the switching frequency of the power-MOSFET-switches is derived from the crystal oscillator. Switching harmonics generated by constant frequency operation are consistent and predictable. When the audio codec is enabled the switching frequency of the converters is synchronised to the audio codec clock to avoid interferences into the audio band. The actual switching frequency can be selected via the I2C-interface between 300 kHz and 580 kHz (for details see DCFR Register in Table 3-3 on page 20). In the PFM operation mode, the switching frequency is controlled by the converters themself, it will be just high enough to service the output load thus resulting in the best possible efficiency at low current loads. PFM mode does not need a clock signal from the crystal oscillator. If both converters do not use the PWMmode, the crystal clock will be shut down as long it is not needed from other internal blocks. The synchronous rectifier bypasses the external Schottky diode to reduce losses caused by the diode forward voltage providing up to 5% efficiency improvement. By default, the P-channel synchronous rectifier switch is turned on when the voltage at pin(s) DCSOn exceeds the converter's output voltage at pin(s) VSENSn and turns off when the inductor current drops below a threshold. If one or both converters are disabled, the corresponding P-channel switch will be turned on, connecting the battery voltage to the DC/ DC converters output voltage at pin VSENSn. However, it is possible to individually disable both synchronous rectifier switches by setting the corresponding bits (bit 8 and 0 in DCCF-register). 2.8.1. DSP Clock The DSP clock has a separate divider. For power conservation it is set to the lowest acceptable rate of the synthesizer clock which is capable to allow the processor core to perform all tasks. 2.8.2. Clock Output at CLKO If the DSP or audio codec functions are enabled (bits 11 or 10 in the Control Register at I2C subaddress 6ahex), the reference clock at pin CLKO is derived from the synthesizer clock. Dependent on the sample rate of the decoded signal a scaler is applied which automatically divides the clockout by 1, 2, or 4, as shown in Table 2-1. An additional division by 2 may be selected by setting bit 17 of the Output Clock Configuration memory cell, OutClkConfig (see Table 3-7 on page 34). The scaler can be disabled by setting bit 8 of this cell. The controlling at OutClkConfig is only possible as long as the DSP is operational (bit 10 of the Control Register). Settings remain valid if the DSP is disabled by clearing bit 10. 2.9. Power Supply Concept The MAS 3587F has been designed for minimal power dissipation. In order to optimize the battery management in portable players, two DC/DC converters have been implemented to supply the complete portable audio player with regulated voltages. 2.9.1. Power Supply Regions The MAS 3587F has five power supply regions. The VDD/VSS pin pair supplies all digital parts including the DSP core, the XVDD/XVSS pin pair is connected to the digital signal pin output buffers, the AVDD0/AVSS0 supply is for the analog output amplifiers, AVDD1/AVSS1 for all other analog circuits like clock oscillator, PLL circuits, system clock synthesizer and A/D and D/A converters. The I2C interface has an own supply region via pin I2CVDD. Connecting this to the microcontroller supply assures that the I2C bus always works as long as the microcontroller is alive so that the operating modes can be selected. Beside these regions, the DC/DC converters have start-up circuits of their own which get their power via pin VSENSx. Micronas 11 MAS 3587F If both DC/DC-converters are off, a high signal may be applied at pin DCEN. This will start the converters in their default mode (PWM with 3.0 V output voltage). The PUP signal will change from low to high when both converters have reached their nominal output voltage and will return to low when both converters output voltages have dropped 200 mV below their programmed output voltage. The signal at pin PUP can be used to control the reset of an external microcontroller (see Section 2.13.2. on page 15 for details on start up procedure). If only DC/DC-converter 1 is used, the output of the unused converter 2 (VSENS2) must be connected to the output of converter 1 (VSENS1) to make the PUP signal work properly. Also, if a DC/DC-converter is not used (no inductor connected), the pin DCSO must be left vacant. ADVANCE INFORMATION battery voltage monitor to I2C interface DCCF (76hex) 15 8 VBAT I2CVDD supply output 1 DCSO2 L1 22 H DC/DC converter 2 DCSG2 D1 VSENS2 set voltage voltage monitor DCEN S PUP Start + - C1 330 F PUP2 + - + - Vin system or crystal clock frequency divider factor 0 R 3 voltage monitor DCFR (77hex) DCCF (76hex) 7 0 DC/DC converter 1 VSS Fig. 2-7: DC/DC converter overview (DCEN input must be connected to pin I2CVDD via the start-up push button) 12 Micronas ADVANCE INFORMATION MAS 3587F 2.9.3. Power Supply Configurations One of the following supply configurations may be used: - Configuration 1: DC/DC 1 (e.g. 2.7 V) supplies controller, flash and MAS 3587F audio parts, DC/DC 2 generates e.g. 2.5 V/3.5 V for the MAS 3587F DSP (see Fig. 2-8). - Configuration 2: All components are powered by an external source, no DC/DC converter is used (see Fig. 2-9). If DC/DC converter 1 is used, it must supply the analog circuits (pins AVDD0, AVDD1) of the MAS 3587F. If the DC/DC converters are not used, pin DCEN must be connected to VSS, DCSOx must be left vacant. e.g. 2.7 V e.g. 3.5 V /2.5 V VSENS1 Flash DC/DC1 on C I2CVDD I2C DSP DC/DC2 on XVDD VDD VSENS2 AVDD0/1 Analog Parts 2.10. Battery Voltage Supervision A battery voltage supervision circuit (at pin VBAT) is provided which is independent of the DC/DC converters. It can be programmed to supervise one or two battery cells. The voltage is measured by subsequently setting a series of voltage thresholds and checking the respective comparison result in register 77hex (see Table 3-3 on page 20). Fig. 2-8: Configuration1: DC/DC-Converter supply Flash VSENS1 DC/DC1 off C I2CVDD I2C DSP DC/DC2 off VDD XVDD VSENS2 External Supply AVDD0/1 e.g. 3.5 V/ 2.7 V Analog Parts Fig. 2-9: Configuration2: External power supply Micronas 13 MAS 3587F 2.11. Interfaces The MAS 3587F uses an I2C control interface, a parallel I/O interface (PIO) for MPEG bit streams and digital audio interfaces for the incomming/outgoing audio data (I2S or similar). Alternatively, SPDIF input and output interfaces can be used. MPEG bit stream input to the decoder is also possible via a second serial input interface. 2.11.1. I2C Control Interface For controlling and program download purposes, a standard I2C slave interface is implemented. A detailed description of all functions can be found in Section 3. ADVANCE INFORMATION In case of the Demand Mode in decoding applications (see Section 2.8.), the signal clock coming from the data source must be higher than the nominal data transmission rate (e.g. 128 kbit/s). Pin EOD is used to interrupt the data flow whenever the input buffer of the MAS 3587F is filled. For controlling details please refer to Table 3-7 on page 34. 2.11.5. Multiline Serial Output (SDO) The serial audio output interface of the MAS 3587F is a standard I2S-like interface consisting of the data lines SOD, the word strobe SOI and the clock signal SOC. It is possible to choose between two standard interface configurations (16-bit data words with word strobe time offset or 32-bit data words with inverted SOI-signal). If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default. 2.11.2. S/PDIF Input Interface The S/PDIF interface receives a one-wire serial bus signal. In addition to the signal input pin SPDI1/SPDI2, a reference pin SPDIR is provided to support balanced signal sources or twisted pair transmission lines. The synchronization time on the input signal is < 50 ms. The SPDIF input signal can also be switched to the SPDO pin. In this case the analog input circuit of the SPDIF inputs (see Fig. 4-16 on page 57) restores the SPDIF input signal to a full swing signal at SPDO. For controlling details please refer to Table 3-7 on page 34. 2.11.6. Parallel Input/Output Interface (PIO) The parallel interface of the MAS 3587F consists of the 8 data lines PI12...PI19 (MSB) and the control lines PCS, PR, PRTR, PRTW, and EOD. It can be used for data exchange with an external memory and for other special purposes as defined by the DSP software. The PIO interface is always used for MPEG-data output. For the handshake protocol please refer to Section 4.6.3.7. For MPEG-data input, the PIO interface is activated by setting bits 9,8 in D0:7f1 to 01. For the handshake protocol please refer to Section 4.6.3.6. 2.11.3. S/PDIF Output The S/PDIF output of the baseband audio signals is provided at pin SPDO. Note that the S/PDIF output is available only for MPEG 1 sampling frequencies (32, 44.1, 48 kHz). 2.11.4. Multiline Serial Audio Input (SDI, SDIB) There are two multiline serial audio input interfaces (SDI, SDIB) each consisting of the three pins SIC, SII, SID, and SIBC, SIBI, SIBD. The firmware supports SDI for audio signals and SDIB for bitstream signals. The interfaces can be configured as continuous bit stream or word-oriented inputs. For the MPEG bitstreams the word strobe pin SIBI must always be connected to VSS, bits must be sent MSB first as created by the encoder. During enabling the DSP and its interfaces, it is strongly recommended to hold the SIBC Pin low. 14 Micronas ADVANCE INFORMATION MAS 3587F 2.13. Default Operation This sections refers to the standard operation mode "power-optimized solution" (see Section 2.9.3.). 2.12. MPEG Synchronization Output The signal at pin SYNC is set to `1' after the internal decoding for the MPEG header has been finished for one frame. The rising edge of this signal can be used as an interrupt input for the controller that triggers the read out of the control information and ancillary data. As soon as the MAS 3587F has received the SYNC reset command (see Section 3.3.1.12. ), the SYNC signal is cleared. If the controller does not issue a reset command, the SYNC signal returns to '0' as soon as the decoding of the next MPEG frame is started. MPEG status and ancillary data become invalid until the frame is completely decoded and the signal at pin SYNC rises again. The controller must have finished reading all MPEG information before it becomes invalid. The MPEG Layer2/3 frame lengths are given in Table 2-2. 2.13.1. Stand-by Functions After applying the battery voltage, the system will remain stand-by, as long as the DCEN pin level is kept low. Due to the low stand-by current of CMOS circuits, the battery may remain connected to DCSOn/VSENSn at all times. 2.13.2. Power-Up of the DC/DC Converters and Reset The battery voltage must be applied to pin DCSOn via the 22-H inductor and, furthermore, to the sense pin VSENSn via a Schottky diode (see Fig. 2-7 on page 12). tframe = 24...72 ms Vh Vl tread Fig. 2-10: Schematic timing of the signal at pin SYNC. The signal is cleared at tread when the controller has issued a Clear SYNC Signal command (see Section 3.3.1.12. ). If no command is issued, the signal returns to '0' just before the decoding of the next MPEG frame. Table 2-2: Frame length in MPEG Layer 2/3 fs/kHz 48 44.1 32 24 22.05 16 12 11.025 8 Frame Length Layer 2 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 36 ms not available not available not available Frame Length Layer 3 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 36 ms 48 ms 52.24 ms 72 ms For start-up, the pin DCEN must be connected via an external "start" push button to the I2CVDD supply, which is equivalent to the battery supply voltage (> 0.9 V) at start-up. The supply at DCEN must be applied until the DC/DC converters have started up (signal at pin PUP) and then removed for normal operation. As soon as the output voltage at VSENSn reaches the default voltage monitor reset level of 3.0 V, the respective internal PUPn bit will be set. When both PUPn bits are set, the signal at pin PUP will go high and can be used to start and reset the microcontroller. Before transmitting any I2C commands, the controller must issue a power-on reset to pin POR. The separate supply pin I2CVDD assures that the I2C interface works indepentently of the DSP or the audio codec. Now the desired supply voltage can be programmed at I2C subaddress 76hex (see Table 3-3 on page 20). The signal at pin PUP will return to low only when both PUPn flags (I2C subaddress 76hex) have returned to zero. Care must be taken when changing both DC/DC output voltages to higher values. In this case, both output voltages are momentarily insufficient to keep the PUPn flags up; the resulting dip in the signal at the PUP pin may in turn reset the microcontroller. To avoid this condition, only one DC/DC output voltage should be changed at a time. Before modifying the second voltage, the microcontroller must wait for the PUPn flag of the first voltage to be set again. The operating mode (pulse width modulation or pulse frequency modulation, synchronized rectifier for higher efficiency) are controlled at I2C subaddress 76hex, the operating frequency at I2C subaddress 77hex. Micronas 15 MAS 3587F 2.13.3. Control of the Signal Processing Before starting the DSP, the controller should check for a sufficient voltage supply (respective flag PUPn at I2C subaddress 76hex). The DSP is enabled by setting the appropriate bit in the Control register (I2C subaddress 6ahex). The nominal frequency of the crystal oscillator must be written into D0:7f3. After an initialization phase of 5 ms, the DSP data registers can be accessed via I2C (see Table 3-3 on page 20). Input and output control is performed via memory location D0:7f1 and D0:7f2. The parallel interface (PIO) is the default setting for compressed data. The decoded audio can be routed to either the SPDIF, the SDO and the analog outputs. The output clock signal at pin CLKO is defined in D0:7f4. The specific settings for audio encoding are written to memory location D0:7f0 (continued). All changes in the D0-memory cells become effective synchronously upon setting the LSB of Main I/O Control (see Table 3-7 on page 34). The common way to start encoding or decoding is to perform all necessary settings and switch on the application by selecting the desired bit(s) in the Application Selection memory cell (D0:7f6) (see Table 3-6 on page 33). The digital volume control (see Table 3-7 on page 34) is applied to the output signal of the DSP. The decoded audio data is by default available at the SPDIF 1 output interface (for MPEG 1 sampling frequencies). The DSP does not have to be started if its functions are not needed, e.g. for routing audio via the A/D and the D/A converters through the codec part of the IC. ADVANCE INFORMATION 2.13.4. Start-up of the Audio Codec (see Table 3-3 on page 20) Before enabling the audio codec, the controller should check for a sufficient voltage supply (respective flag PUPn at I2C subaddress 76hex). The audio codec is enabled by setting the appropriate bit at the Control register (I2C subaddress 6ahex). After an initialization phase of 5 ms, the DSP data registers can be accessed via I2C. The A/D and the D/A converters must be switched on explicitly (00 00hex at I2C subaddress 6chex). The D/A converters may either accept data from the A/D converters or the output of the DSP, or a mix of both (register 00 06hex and 00 07hex at I2C subaddress 6chex). Finally, an appropriate output volume (00 10hex at I2C subaddress 6chex) must be selected. 2.13.5. Power-Down (see Table 3-3 on page 20) All analog outputs should be muted and the A/D and the D/A converters must be switched off (register 00 10hex and 00 00hex at I2C subaddress 6chex). The DSP and the audio codec must be disabled (clear DSP_EN and CODEC_EN bits in the Control register, I2C subaddress 6ahex). By clearing both DC/DC enable flags in the Control register (I2C subaddress 6ahex), the microcontroller can power down the complete system. 16 Micronas ADVANCE INFORMATION MAS 3587F Table 3-2: I2C Subaddresses Subaddress (hex) I2CRegister Name Function 3. I2C Interface 3.1. General 3.1.1. Device Address Controlling the MAS 3587F is done via an I2C slave interface. The device addresses are 3C/3Ehex (device write) and 3D/3Fhex (device read) as shown in Table 3- 1. The device address pair 3C/3Dhex applies if the DVS pin is connected to VSS, the device address pair 3E/ 3Fhex applies if the DVS pin is connected to VDD. Table 3-1: I2C device address Direct Configuration 6A 76 CONTROL DCCF Controller writes to MAS 3587F control register Controller writes to first DC/DC configuration register Controller writes to second DC/DC config reg. 77 DCFR A7 0 A6 0 A5 1 A4 1 A3 1 A2 1 A1 DVS W/R 0/1 DSP Core Access 68 69 DATA (WRITE) DATA (READ) I2C clock synchronization is used to slow down the interface if required. 3.1.2. I2C Registers and Subaddresses The interface uses one level of subaddresses. The MAS 3587F interface has 7 subaddresses allocated for the corresponding I2C registers. The registers can be divided into three categories as shown in Table 3-2. The address 6Ahex is used for basic control, i.e. reset and task select. The other addresses are used for data transfer from/to the MAS 3587F. The I2C registers of the MAS 3587F are 16 bits wide, the MSB is denoted as bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, MSB sent first); thus, for each register access, two 8-bit data words must be sent/received via I2C bus. Controller writes to MAS 3587F DSP Controller reads from MAS 3587F DSP Codec Access 6C 6D CODEC (WRITE) CODEC (READ) Controller writes to MAS 3587F codec register Controller reads from MAS 3587F codec register Micronas 17 MAS 3587F 3.1.3. Naming Convention The description of the various controller commands uses the following formalism: - Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don't care - A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble. - Data values in nibbles are always shown in hexadecimal notation. - A hexadecimal 20-bit number d is written, e.g. as d = 17C63hex, its five nibbles are d0 = 3hex, d1 = 6hex, d2 = Chex, d3 = 7hex, and d4 = 1hex. - Variables used in the following descriptions: I2C address: DW 3C/3Ehex DR 3D/3Fhex DSP core: data_write 68hex data_read 69hex Codec: codec_write 6Chex codec_read 6Dhex ADVANCE INFORMATION - Bus signals S Start P Stop A ACK = Acknowledge N NAK = Not acknowledge W Wait = I2C Clockline is held low, while the MAS 3587F is processing the I2C command - Symbols in the telegram examples < Start Condition > Stop dd data bytes xx ignore All telegram numbers are hexadecimal, data originating from the MAS 3587F are greyed. Example: Example: I2C write access S DW A subaddress A high data word A low data word A P Example: I2C read access S DW A subaddress A S DR A high data word low data word A N P SDA SCL S 1 0 P A N S P = = = = 0 (ACK) 1 (NAK) Start Stop Fig. 3-1: Example of an I2C bus protocol for the MAS 3587F (MSB first; data must be stable while clock is high) 18 Micronas ADVANCE INFORMATION MAS 3587F 3.2. Direct Configuration Registers The task selection of the DSP and the DC/DC converters are controlled in the direct configuration registers Control, DCCF, and DCFR. 3.2.1. Write Direct Configuration Registers S DW A subaddress A d3,d2 A d1,d0 A P The write protocol for the direct configuration registers only consists of device address, subaddress and one 16-bit data word. 3.2.2. Read Direct Configuration Register 1) send subaddress S DW A subaddress A P 2) get register value S DW A subaddress A S DR d3,d2 A A d1,d0 N P To check the PUP1 and PUP2 power-up flags, it is necessary to read back the content of the direct configuration registers. Micronas 19 MAS 3587F Table 3-3: Direct Configuration Registers I2C Subaddress (hex) 6A Function ADVANCE INFORMATION Name Control Register (reset value = 3000hex) bit[15:14] Code 00 01 10 11 Analog Supply Voltage Range AGNDC 1.1 V 1.3 V 1.6 V reserved recommended for voltage range of AVDD 2.0 ... 2.4 V (reset) 2.4 ... 3.0 V 3.0 ... 3.6 V reserved CONTROL Higher voltage ranges permit higher output levels and thus a better signal-tonoise ratio. bit[13] bit[12] enable DC/DC 2 (reset=1) enable DC/DC 1 (reset=1) Both DC/DC converters are switched on by default. bit[11] bit[10] enable and reset audio codec enable and reset DSP core For normal operation (MPEG-decoding and D/A conversion), both, the DSP core and the audio codec have to be enabled after the power-up procedure. The DSP can be left off if an audio signal is routed from the analog inputs to the analog outputs (set bit[15] in codec register 00 0Fhex). The audio codec can be left off if the DSP uses digital inputs and outputs only. bit[9] bit[8] bit[7] 1) bit[6:0] 1) reset codec reset DSP core reserved, must be set to zero reserved, must be set to zero usage in the next version: enable XTAL input clock divider (extended crystal range up to 28 MHz) 20 Micronas ADVANCE INFORMATION MAS 3587F Table 3-3: Direct Configuration Registers I2C Subaddress (hex) 76 Function Name DCCF Register (reset = 5050hex) DC/DC Converter 2 bit[15] bit[14:11] PUP2: Voltage monitor 2 flag (readback) Voltage between VSENS2 and DCSG2 Code 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 00011) 00001) bit[10] Mode 1 0 Nominal output volt. 3.5 V 3.4 V 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V 2.0 V set level of PUP2 3.4 V 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V 2.0 V 1.9 V reset level of PUP2 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V (reset) 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V 2.0 V 1.9 V 1.8 V DCCF Pulse frequency modulation (PFM) Pulse width modulation (PWM) (reset) bit[9] bit[8] reserved, must be set to zero Disable synchronized rectifier 1 disable synchronized recitifier 0 enable synchronized recitifier (reset) The DC/DC converters are up-converters only. Thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. 1) refer to Section 4.6.2. on page 59 Micronas 21 MAS 3587F Table 3-3: Direct Configuration Registers I2C Subaddress (hex) 76 (continued) ADVANCE INFORMATION Function Name DC/DC Converter 1 bit[7] bit[6:3] bit[2] PUP1: Voltage monitor 1 flag (readback) Voltage between VSENS1 and DCSG1 (see table above) Mode 1 0 Pulse frequency modulation (PFM) Pulse width modulation (PWM) (reset) bit[1] bit[0] reserved, must be set to zero Disable synchronized rectifier 1 disable synchronized recitifier 0 enable synchronized recitifier (reset) Note, that the reference voltage for DC/DC converter 1 is derived from the main reference source supplied via pin AVDD1. Therefore, if this DC/DC converter is used, its output must be connected to the analog supply. The DC/DC converters are up-converters only. Thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. 22 Micronas ADVANCE INFORMATION MAS 3587F Table 3-3: Direct Configuration Registers I2C Subaddress (hex) 77 Function Name DCFR Register (reset = 00hex) Battery Voltage Monitor bit[15] Comparison result (readback) 1 input voltage at pin VBAT above defined threshold 0 input voltage at pin VBAT below defined threshold Number of battery cells 0 1 cell (range 0.8...1.5 V) (reset) 1 2 cells (range 1.6...3.0 V) Voltage threshold level 1 cell 2 cells 1111 1.5 3.0 V 1110 1.45 2.9 V ... 0010 0.85 1.7 V 0001 0.8 1.6 V 0000 Battery voltage supervision off (reset) Reserved, must be set to 0 DCFR bit[14] bit[13:10] bit[9:8] The result is stable after 1 ms after enabling. The setup time for switching between two thresholds is negligibly small. For power management reasons, the battery voltage monitor should be switched off by setting bit[13:10] to zero when the measurement is completed. DC/DC Converter Frequency Control (PWM) bit[7:4] bit[3:0] Reserved, must be set to 0 Frequency of DC/DC converter Reference: 24.576 0111 315.1 0110 323.4 0101 332.1 0100 341.3 0011 351.1 0010 361.4 0001 372.4 0000 384.0 1111 396.4 1110 409.6 1101 423.7 1100 438.9 1011 455.1 1010 472.6 1001 491.5 1000 512.0 22.5792 18.432 MHz 289.5 297.3 kHz 297.1 307.2 kHz 305.1 317.8 kHz 313.6 329.1 kHz 322.6 341.3 kHz 332.0 354.5 kHz 342.1 368.6 kHz 352.8 384.0 kHz (reset) 364.2 400.7 kHz 376.3 418.9 kHz 389.3 438.9 kHz 403.2 460.8 kHz 418.1 485.1 kHz 434.2 512.0 kHz 451.6 542.1 kHz 470.4 576.0 kHz If the audio codec is not enabled (bit 11 of the Control register at I2C-subaddress 6Ahex is zero), the clock for the DC/DC converters is directly derived from the crystal frequency (nominal 18.432 MHz). Otherwise, the synthesizer clock is used as the reference (please refer to the respective column in Table 2-1 on page 10). Micronas 23 MAS 3587F 3.3. DSP Core The DSP Core of the MAS 3587F has two RAM banks denoted D0 and D1. The word size is 20 bits. All RAM addresses can be accessed in a 20-bit or a 16-bit mode via I2C bus. For fast access of internal DSP states, the processor core also has an address space of 256 data registers. All register and RAM addresses are given in hexadecimal notation. ADVANCE INFORMATION also provides a download option for alternative software modules. The MAS 3587F firmware scans the I2C interface periodically and checks for pending or new commands. However, due to some time critical firmware parts, a certain latency time for the response has to be expected. The theoretical worst case response time does not exceed 4 ms. However, the typical response time is less than 0.5 ms. Table 3-4 gives an overview over the different commands which the DSP Core receives via the I2C data register. The "Code" is always the first data nibble transmitted after the "data_write" subaddress byte. A second auxiliary code nibble is used for the short memory (16-bit) access commands. Due to the 16-bit width of the I2C data register, all actions transmit telegrams with multiples of 16 data bits. 3.3.1. Access Protocol The access of the DSP Core in the MAS 3587F uses a special command syntax. The commands are executed by the DSP during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. These I2C commands allow the controller accessing the internal DSP registers and RAM cells and thus, monitoring internal states and setting the parameters for the DSP firmware. This access S DW W A $68 W A code , ... A ... , ... A ... , ... Fig. 3-2: General core access protocol Table 3-4: Basic controller command codes Code (hex) 0...3 5 6 A B C D E F Command Run Read Ancillary Data Fast Program Download Read from Register Write to Register Read D0 Memory Read D1 Memory Write D0 Memory Write D1 Memory Function Start execution of an internal program. Run with start address 0 means freeze the operating system. The controller reads a block of MPEG Ancillary Data from the MAS 3587F The controller downloads custom software via the PIO interface The controller reads an internal register of the MAS 3587F The controller writes an internal register of the MAS 3587F The controller reads a block of the DSP memory The controller reads a block of the DSP memory The controller writes a block of the DSP memory The controller writes a block of the DSP memory 24 Micronas ADVANCE INFORMATION MAS 3587F 3.3.1.1. Run and Freeze S DW W A $68 W A a3,a2 A a1,a0 W A P The Run command causes the start of a program part at address a = (a3,a2,a1,a0). Since nibble a3 is also the command code (see Table 3-4), it is restricted to values between 0 and 3. If the start address is 1000hex a < 3FFFhex and the respective RAM area has been configured as program RAM (see Table 3-5 on page 32), the MAS 3587F continues execution with a custom program already downloaded to this area. Example 1: Start program execution at address 345hex: 3.3.1.2. Read Register (Code Ahex) 1) send command S DW W A $68 W A a,r1 A r0,0 W A P 2) get register value S DW W A $68 x,x W A A S DR W A W A A x,d4 d3,d2 d1,d0 W N P Some registers (r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others control the internal program flow. In contrast to memory cells, registers cannot be accessed as a block but must always be addressed individually. Example: Read the content of the PIO data register (C8hex): define register and read Micronas 25 MAS 3587F 3.3.1.3. Write Register (Code Bhex) S ADVANCE INFORMATION DW W A $68 W A b,r1 d3,d2 A A r0,d4 d1,d0 W W A A P The controller writes the 20-bit value (d = d4,d3,d2, d1,d0) into the MAS 3587F register (r = r1,r0). Example: Writing the value 81234hex into the register with the number AAhex: 3.3.1.4. Read D0 Memory (Code Chex) The MAS 3587F has 2 memory areas of 2048 words called D0 and D1 memory. Both memory areas have different read and write commands. All D0/D1 memory addresses are given in hexadecimal notation. 1) send command S DW W A $68 W A c,0 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P 2) get memory value S DW W A $69 x,x W A A S DR W A W A A x,d4 d3,d2 d1,d0 W A ...repeat for n data values... x,x A x,d4 W A d3,d2 A d1,d0 W N P The Read D0 Memory command gives the controller access to all 20 bits of D0 memory cells of the MAS 3587F. The telegram to read 3 words starting at location D0:100 is 26 Micronas ADVANCE INFORMATION MAS 3587F 3.3.1.5. Short Read D0 Memory (Code C4hex) Because most cells in the user interface are only 16 bits wide, it is faster and more convenient to access the memory locations with a special 16 bit mode for reading: 1) send command S DW W A $68 W A c,4 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P 2) get memory value S DW W A $69 W A S DR A W A W A d3,d2 d1,d0 ...repeat for n data values... d3,d2 A d1,d0 W N P This command is similar to the normal 20 bit read command and uses the same command code Chex, however it is followed by a 4hex rather than a 0hex. 3.3.1.6. Read D1 Memory (Code Dhex) 1) send command S DW W A $68 W A d,0 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P 2) get memory value S DW W A $69 x,x W A A S DR W A W A A x,d4 d3,d2 d1,d0 W A ...repeat for n data values... x,x A x,d4 W A d3,d2 A d1,d0 W N P The Read D1 Memory command is provided to get information from D1 memory cells of the MAS 3587F. Micronas 27 MAS 3587F 3.3.1.7. Short Read D1 Memory (Code D4hex) 1) send command S ADVANCE INFORMATION DW W A $68 W A d,4 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P 2) get memory value S DW W A $69 W A S DR A W A W A d3,d2 d1,d0 ...repeat for n data values... d3,d2 A d1,d0 W N P The Short Read D1 Memory command works similar to the Read D1 Memory command but with the code Dhex followed by a 4hex. Example: Read 16 bits of D1:123 has the following I2C protocol: read 16 bits from D1 1 word to be read start address start reading 3.3.1.8. Write D0 Memory (Code Ehex) S DW W A $68 W A e,0 n3,n2 a3,a2 0,0 d3,d2 A A A A A 0,0 n1,n0 a1,a0 0,d4 d1,d0 W W W W W A A A A A ...repeat for n data values... 0,0 d3,d2 A A 0,d4 d1,d0 W W A A P With the Write D0 Memory command n 20-bit memory cells in D0 can be initialized with new data. Example: Write 80234hex to D0:456 has the following I2C protocol: write D1 memory 1 word to write start address value = 80234hex 28 Micronas ADVANCE INFORMATION MAS 3587F 3.3.1.9. Short Write D0 Memory (Code E4hex) S DW W A $68 W A e,4 n3,n2 a3,a2 d3,d2 A A A A 0,0 n1,n0 a1,a0 d1,d0 W W W W A A A A ...repeat for n data values... d3,d2 A d1,d0 W A P For faster access only the lower 16 bits of each memory cell are accessed. The 4 MSBs of the cell are cleared. 3.3.1.10. Write D1 Memory (Code Fhex) S DW W A $68 W A f,0 n3,n2 a3,a2 0,0 d3,d2 A A A A A 0,0 n1,n0 a1,a0 0,d4 d1,d0 W W W W W A A A A A ...repeat for n data values... 0,0 d3,d2 A A 0,d4 d1,d0 W W A A P For further details, see the Write D0 Memory command. 3.3.1.11. Short Write D1 Memory (Code F4hex) S DW W A $68 W A f,4 n3,n2 a3,a2 d3,d2 A A A A 0,0 n1,n0 a1,a0 d1,d0 W W W W A A A A ...repeat for n data values... d3,d2 A d1,d0 W A P Only the 16 lower bits of each memory cell are written, the upper 4 bits are cleared. Micronas 29 MAS 3587F 3.3.1.12. Clear SYNC Signal (Code 5hex) S ADVANCE INFORMATION DW W A $68 W A 5,0 A 0,0 W A P After the successful decoding of an MPEG frame the signal at pin SYNC rises and thus generates an interrupt event for the microcontroller. Issuing this command lets the signal at pin SYNC return to '0'. 3.3.1.13. Default Read The Default Read command is the fastest way to get information from the MAS 3587F. Executing the Default Read in a polling loop can be used to detect a special state during decoding. S DW W A $69 W A S DR d3,d2 W A A d1,d0 W N P The Default Read command immediately returns the lower 16 bit content of a specific RAM location as defined by the pointer D0:ffb. The pointer must be loaded before the first Default Read action occurs. If the MSB of the pointer is set, the pointer refers to a memory location in D1 rather than to one in D0. Example: For watching D1:123 the pointer D0:ffb must be loaded with 8123hex: write to D0 memory 1 word to write start address ffb value = 8... ...0123hex Now Default Read commands can be issued as often as desired: 'HIDXOW 5HDG command 16 bit content of the address as defined by the pointer ... and do it again 30 Micronas ADVANCE INFORMATION MAS 3587F 3.3.1.14. Fast Program Download S DW W A $69 W A 6,n2 a3,a2 A A n1,n0 a1,a0 W W A A P The Fast Program Download command introduces a data transfer via the parallel port. n = n2,n1,n0 denotes the number of 20-bit data words to be transferred, a = a3,a2,a1,a0 gives the start address. The data at the PIO port must be padded with three 0-nibbles to get multiples of 16 bits. The download must be initiated in the following sequence: - Issue Freeze command - Stop all DMA transfers - Issue Fast Program Download command - Download code via PIO interface - Switch appropriate memory area to act as program RAM (register EDhex) - Issue Run command to start program execution at entry point of downloaded code Example for Fast Program Download command: Download 4 words starting at D0:1400: (stop all data transfers) )UHH]H initiate download of 4 words start at address D0:1000 Now transfer 8-bit words via the parallel PIO port: 0,0 0,0 0,0 0,0 0,d4 0,d4 0,d4 0,d4 d3,d2 d3,d2 d3,d2 d3,d2 d1,d0 d1,d0 d1,d0 d1,d0 reconfigure memory from D0:1000 to D0:17ff start program execution at address D0:1000 3.3.1.15. Serial Program Download Program downloads may also be performed via the I2C interface by using the Write D0/1 Memory commands. A similar command sequence as in the Fast Program Download (stop transfers, Freeze...) applies. Micronas 31 MAS 3587F 3.3.2. List of DSP Registers ADVANCE INFORMATION Table 3-5 lists the registers used in the standard firmware (MPEG) and for the download option (Download). Note: Registers not given in the tables must not be written. Table 3-5: DSP Register Table Address (hex) 6B R/W R/W FunctionMode Configuration of Variable RAM Areas bit[19] bit[18] bit[17] bit[16] Affected RAM area D0:800 ... D0:BFF D0:C00 ... D0:FFF D1:800 ... D1:BFF D1:C00 ... D1:FFF Download Default (hex) 0000 Name PSelect_Shadow This register is used to switch four RAM areas from data to program usage and thus enabling the DSP's program counter to access downloaded program code stored at these locations. For normal operation (firmware in ROM) this register must be kept to zero. For details of program code download please refer to Section 3.3.1.14. 56 R S/PDIF1) Input Channel Status Bits bit[15:0] 1) MPEG 0000 SPIChannelStatus channel status bits of incoming signal. IEC 958 Amendment1, "Digital Audio Interface" 3.3.3. List of DSP Memory Cells Among the user interface control memory cells there are some which have a global meaning and some which control application specific parts of the DSP core. In the tables below this is reflected by the keywords All, Encoder and Decoder. - check AppRunning for "0" - apply necessary/wanted Control settings - write value to AppSelect according to Table 3-6 3.3.3.2. Application Specific Control The configuration of the MPEG Encoder and Decoder firmware is done via the control memory cells described in Table 3-7. The changes applied to any of the control memory cells have to be validated by setting bit[0] of memory cell Main I/O Control except when the application is started by writing the AppSelect memory cell. The validate bit will be reset automatically after the changes have been taken over by the DSP. The status memory cells are used to read the encoder/ decoder status and to get additional MPEG bitstream information. Note: Memory cells not given in the tables must not be written. 3.3.3.1. Application Select and Running The AppSelect cell is a global user interface configuration cell, which has to be written in order to start a specific application. The AppRunning cell is a global user interface status cell, which indicates, which application loop is actually running. The meaning of the bits in both cells is given in Table 3-6. Following steps have to be performed to switch between applications: - write "0" to AppSelect 32 Micronas ADVANCE INFORMATION MAS 3587F Table 3-6: Application Control and Status Memory Address (hex) D0:7f6 Function Name Application Selection All AppSelect AppSelect is used for selecting an application. This is done by setting the appropriate bit to one. It is principally allowed to set more than one bit to one, e.g. setting AppSelect to 0xc will select all MPEG audio decoders. The autodetection feature will automatically detect the Layer 2 or Layer 3 data. When bit[0]/bit[1] are asserted, the DSP begins to loop inside the OS loop/Top Level loop respectively. It is recomended to perform the necessary settings for the firmware before the application is started by writing this memory cell. bit[6] bit[3] bit[2] bit[1] bit[0] D0:7f7 MPEG Layer 3 Encoder MPEG Layer 3 Decoder MPEG Layer 2 Decoder Top Level Operating System All AppRunning Application Running The AppRunning cell is a global user interface status cell, that indicates which application loop is actually running. After writing AppSelect, it has to be checked whether the appropriate bit(s) in the AppRunning cell is set, prior to any changes in the configuration registers or memory cells bit[6] bit[3] bit[2] bit[1] bit[0] D0:7f0 MPEG Layer 3 Encoder MPEG Layer 3 Decoder MPEG Layer 2 Decoder Top Level Operating System Encoder EncoderControl Encoder Control (reset = a0264hex) EncoderControl is used for selecting the quality level, sample frequency and other options for encoding. bit[19:17] Quality Setting 000 0 lowest bitrate / quality 001 1 010 2 011 3 100 4 101 (reset) 5 recommended quality The maximum bitrate is limited to 192 kbit/s, whereas the average bitrate highly depends on the audio source. At the recommanded quality setting and a sampling rate of 44.1 kHz, the average bitrate is typically found in the range from 130 to 140 kBit/s. 110 6 111 7 highest bitrate / quality Reserved, must be set to zero bit[16:12] ... Micronas 33 MAS 3587F Table 3-7: D0 Control Memory Cells Memory Address (hex) D0:7f0 (continued) ADVANCE INFORMATION Function Name bit[11:10] Sampling Frequency (kHz) 00 (reset) 01 10 11 MPEG Selection 0 MPEG 2 1 (reset) MPEG 1 MPEG 1 44.1 48 32 reserved MPEG 2 22.05 24 16 bit[9] Bit[11:9] are only evaluated for SDI audio input (selected in D0:7f1, bit[9:8]). In case of S/PDIF audio input, MPEG 1 is used and the sampling frequency is auto detected. bit[8] CRC protection 0 (reset) enable CRC protection 1 disable CRC protection Channel Mode 00 reserved 01 (reset) joint stereo 10 reserved 11 single channel Channel Mode Extension (for joint stereo) 0 disable MS-Stereo encoding 1 (reset) enable MS-Stereo encoding Reserved, must be set to zero Copyright 0 (reset) 1 bit stream is not copyright protected bit stream is copyright protected bit[7:6] bit[5] bit[4] bit[3] bit[2] Copy / Original 0 bit stream is a copy 1 (reset) bit stream is an original Emphasis 00 (reset) 01 10 11 none 50/15 s reserved CCITT J.17 bit[1:0] 34 Micronas ADVANCE INFORMATION MAS 3587F Table 3-7: D0 Control Memory Cells Memory Address (hex) D0:7f1 Function Name Main I/O Control (reset = 124hex) All IOControlMain IOControlMain is used for selecting/deselecting the appropriate data input interface and for setting up the serial data output interface. In serial input mode the coded audio data (Layer 2, Layer 3) is expected at the serial input interface SDIB. In the 8-bit-parallel input mode (default) the PIO pins PI[19:12] are used. bit[15] bit[14] Reserved, must be set to zero Invert serial output clock (SOC) 0 (reset) do not invert SOC 1 invert SOC Reserved, must be set to zero Serial data output delay 0 (reset) no additional delay (reset) 1 additional delay of data related to word strobe Reserved, must be set to zero Encoder: Audio Input Select 00 SDI input with PLL 01 (reset) SDI input without PLL 10 S/PDIF input 11 reserved Decoder: Data Input Select 00 serial input at interface B 01 (reset) parallel input at PIO pins PI[19...12] 10 reserved 11 reserved bit[7] Encoder: Invert serial input clock (SIC) 0 (reset) do not invert SIC 1 invert SIC Encoder: Serial data input delay 0 (reset) no additional delay (reset) 1 additional delay of data related to word strobe SDO Word Strobe Invert 0 do not invert 1 (reset) invert outgoing word strobe signal Bits per Sample at SDO 0 (reset) 32 bits/sample 1 16 bits/sample Encoder: Clock setting 0 (reset) MPEG 1 1 MPEG 2 May only be set for MPEG 2 encoding. Serial data input interface B clock invert (pin SIBC) 0 not inverted (data latched at rising clock edge) 1 (reset) incoming clock signal is inverted (data latched at falling clock edge) bit[13:12] bit[11] bit[10] bit[9:8] bit[6] bit[5] bit[4] bit[3] bit[3] bit[2] ... Micronas 35 MAS 3587F Table 3-7: D0 Control Memory Cells Memory Address (hex) D0:7f1 (continued) ADVANCE INFORMATION Function Name Main I/O Control, continued bit[1] Decoder: 0 (reset) 1 DEMAND MODE (PLL off, MAS 3587F is clock master) BROADCAST MODE (PLL on, clock of MAS 3587F locks on data stream) Encoder: SDI Word Strobe Invert 0 (reset) do not invert 1 invert incoming word strobe signal Note: L/R channel swap is present today with the reset value. Correct value for encoder is "1". Correct default channel setting will be implemented in future versions. bit[0] Validate 0 (reset) 1 changes in control memory will be ignored changes in control memory will become effective Bit[0] is reset after the DSP has recognized the changes. The controller should set this bit after the other D0 control memory cells have been initialized with the desired values. D0:7f2 Interface Status Control (reset = 05hex) All InterfaceControl This control cell allows to enable/disable the data I/O interfaces. In addition, the clock of the output data interfaces, S/PDIF and SDO, can be set to a lowimpedance mode. bit[6] S/PDIF input selection 0 (reset) select S/PDIF input 1 1 select S/PDIF input 2 Enable/disable S/PDIF output 0 (reset) enable S/PDIF output 1 S/PDIF output off (tristate) bit[5] Note that S/PDIF audio output is only available for MPEG 1 (sampling frequencies 32, 44.1 and 48 kHz) bit[4] bit[3] Reserved, must be set to zero Enable/disable serial data output SDO 0 SDO on 1 (reset) SDO off Output clock characteristic (SDO and S/PDIF outputs) 0 low impedance 1 (reset) high impedance reserved, must be set to zero Enable/disable external serial data input SDI 0 use external audio source (SDI) 1 (reset) use internal A/D converter as audio source bit[2] bit[1] bit[0] Both digital outputs, S/PDIF and SPO, and the D/A converters may use the outgoing audio independent of each other. Changes at this memory address must be validated by setting bit [0] of D0:7f1. 36 Micronas ADVANCE INFORMATION MAS 3587F Table 3-7: D0 Control Memory Cells Memory Address (hex) D0:7f3 Function Name Oscillator Frequency (reset = 18432dec) bit[19:0] oscillator frequency in kHz All OfreqControl In order to achieve a correct internal operating frequency of the DSP, the nominal crystal frequency has to be deposited into this memory cell. Changes at this memory address must be validated by setting bit 0 of D0:7f1. D0:7f4 Output Clock Configuration (pin CLKO) (reset = 80000hex) bit[19] CLKO configuration 0 output clock signal at CLKO 1 (reset) CLKO is tristate All OutClkConfig The CLKO output pin of the MAS 3587F can be disabled via bit [19]. bit[18] bit[17] Reserved, must be set to zero Additional division by 2 if scaler is on (bit[8] cleared) 0 (reset) oversampling factor 512/768 1 oversampling factor 256/384 Reserved, must be set to zero Output clock scaler 0 (reset) set output clock according to audio sample rate (see Table 2-1) 1 output clock fixed at 24.576 or 22.5792 MHz bit[16:9] bit[8] For a list of output frequencies at pin CLKO please refer to Table 2-1. bit[7:0] reserved, must be set to zero Changes at this memory address must be validated by setting bit[0] of D0:7f1. D0:7f8 D0:7f9 S/PDIF1) channel status bits category code setting (reset = 8004hex) All Soft Mute (reset = 0hex) bit[19:0] D0:7fc D0:7fd D0:7fe D0:7ff 1) SpdOutBits SoftMute Decoder mute off mute on Decoder Decoder Decoder Decoder 0 (reset) 1 Volume output control: left left gain (reset = 80000hex) Volume output control: left right gain (reset = 0hex) Volume output control: right left gain(reset = 0hex) Volume control: right right gain (reset = 80000hex) out_LL out_LR out_RL out_RR IEC 958 Amendment1, "Digital Audio Interface" Micronas 37 MAS 3587F Table 3-8: D0 Status Memory Cells Memory Address D0:FD0 Function MPEG Frame Counter bit[19:0] number of MPEG frames after synchronization ADVANCE INFORMATION Name All MPEGFrameCount The counter will be incremented with every new frame that is encoded/ decoded. With an invalid MPEG bit stream at its input while decoding (e.g. an invalid header is detected), the MAS 3587F resets the MPEGFrameCount to `0'. In encoding mode, the counter is reset on audio data timeouts and after restarting the encoder. D0:FD1 MPEG Header and Status Information bit[15] bit[14:13] reserved, must be set to zero MPEG ID, Bits 12, 11 of the MPEG header 00 MPEG 2.5 (decoding only) 01 reserved 10 MPEG 2 11 MPEG 1 Bits 14 and 13 of the MPEG header 00 reserved 01 Layer 3 10 Layer 2 (decoding only) 11 Layer 1 (decoding only) CRC Protection 0 bitstream protected by CRC 1 bitstream not protected by CRC Reserved CRC error (decoding only) 0 no CRC error 1 CRC error Invalid frame (decoding only) 0 no invalid frame 1 invalid frame All MPEGStatus1 bit[12:11] bit[10] bit[9:2] bit[1] bit[0] This location contains bits 15...11 of the original MPEG header and other status bits. It will be set each frame directly after the header has been encoded/ decoded from the bit stream. 38 Micronas ADVANCE INFORMATION MAS 3587F Table 3-8: D0 Status Memory Cells Memory Address D0:FD2 Function MPEG Header Information bit[15:12] MPEG Layer 2/3 Bitrate All Name MPEGStatus2 MPEG1, L2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 bit[11:10] free 32 48 56 64 80 96 112 128 160 192 224 256 320 384 forbidden MPEG1, L3 free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 forbidden MPEG2, L2/3 free 8 16 24 32 40 48 56 64 80 96 112 128 144 160 forbidden Sampling frequencies in Hz MPEG1 00 01 10 11 44100 48000 32000 reserved MPEG2 22050 24000 16000 reserved MPEG2.5 11025 12000 8000 reserved bit[9] bit[8] bit[7:6] Padding Bit reserved Mode 00 01 10 11 stereo joint_stereo (intensity stereo / m/s stereo) dual channel single channel bit[5:4] Mode extension (applies to joint stereo only) intensity stereo off on off on m/s stereo off off on on 00 01 10 11 bit[3] bit[2] Copyright Protect Bit 0/1 not copyright protected/copyright protected Copy/Original Bit 0/1 bitstream is a copy/bitstream is an original ... Micronas 39 MAS 3587F Table 3-8: D0 Status Memory Cells Memory Address D0:FD2 (continued) ADVANCE INFORMATION Function MPEG Header Information, continued bit[1:0] Emphasis, indicates the type of emphasis 00 none 01 50/15 s 10 reserved 11 CCITT J.17 Name MPEGStatus2 This memory cell contains the 16 LSBs of the MPEG header. It will be set directly after synchronizing to the bit stream. D0:FD3 MPEG CRC Error Counter Decoder CRCErrorCount The counter will be increased by each CRC error detected in the MPEG bisstream. It will not be reset when losing the synchronization. D0:FD4 Number of Bits in Ancillary Data Number of valid ancillary bits in the current MPEG frame. D0:FD5 ... D0:FF1 Ancillary Data (see Section 3.3.4. on page 40). Decoder Decoder NumberOfAncillaryBits AncillaryData 3.3.4. Ancillary Data The memory fields D0:FD5...D0:ff1 contain the ancillary data. It is organized in 28 words of 16 bit each. The last ancillary bit of a frame is placed at bit 0 in D0:FD5. The position of the first ancillary data bit received can be located via the content of NumberOfAncillaryBits because int[(NumberOfAncillaryBits-1)/16] + 1 of memory words are used. Example: First get the content of 'NumberOfAncillaryBits' Assume that the MAS 3587F has received 19 ancillary data bits. Therefore, it is necessary to read two 16-bit words: Short Read from D0 The first bit received from the MPEG source is at position 2 of D0:FD6; the last bit received is at the LSB of D0:fd5. 40 Micronas ADVANCE INFORMATION MAS 3587F Table 3-9: Settings for the digital volume matrix Memory Name Stereo (default) Mono left Mono right D0:354 LL D0:355 LR 0 D0:356 RL 0 0 D0:357 RR 3.3.5. DSP Volume Control The digital baseband volume matrix is used for controlling the digital gain of the decoder as shown in Fig. 3- 3. This volume control is effective on both, the digital audio output and the data stream to the D/A converters. The values are in 20-bit 2's complement notation. Table 3-9 shows the proposed settings for the 4 volume matrix coefficients for stereo, left and right mono. The gain factors are given in fixed point notation (-1.0x219 = 80000hex). The DSP volume control is available in Decoder Mode only. -1.0 -1.0 0 -1.0 0 -1.0 0 -1.0 -1.0 left audio -1 LL + If channels are mixed, care must be taken to prevent clipping at high amplitudes. Therefore the sum of the absolute values of coefficients for one output channel should be less than 1.0. For normal operating conditions it is recommended to use the main volume control of the audio codec instead (register 00 10hex of the audio codec). -1 LR -1 RL right audio -1 RR + Fig. 3-3: Digital volume matrix Table 3-10: Content of D0:fd5 after reception of 19 ancillary bits. D0:fd5 Ancillary Data MSB 4th bit 14 5th bit 13 6th bit 12 ... 11 ... 10 ... 9 ... 8 ... 7 ... 6 ... 5 ... 4 ... 3 ... 2 17th bit 1 18th bit LSB last bit Table 3-11: Content of D0:fd6 after reception of 19 ancillary bits. D0:fd6 Ancillary Data MSB x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 first bit 1 2nd bit LSB 3rd bit Micronas to digital output and D/A from MPEG decoder 41 MAS 3587F 3.4. Audio Codec Access Protocol ADVANCE INFORMATION The MAS 3587F has 16-bit wide registers for the control of the audio codec. These registers are accessed via the I2C subaddresses codec_write (6Chex) and codec_read (6Dhex). 3.4.1. Write Codec Register S DW W A $6C A r3,r2 d3,d2 A A r1,r0 d1,d0 A A P The controller writes the 16-bit value (d = d3,d2,d1,d0) into the MAS 3587F codec register (r = r3,r2,r1,r0). A list of registers is given in Table 3-12. Example: Writing the value 1234hex into the codec register with the number 00 1Bhex: 3.4.2. Read Codec Register 1) send command S DW W A $6C A r3,r2 A r1,r0 A P 2) get register value S DW W A $6D A S DR A W A N P d3,d2 d1,d0 Reading the codec registers also needs a set-up for the register address and an additional start condition during the actual read cycle. A list of registers is given in Table 3-13. 42 Micronas ADVANCE INFORMATION MAS 3587F 3.4.3. Codec Registers Table 3-12: Codec control registers on I2C subaddress 6Chex Register Address (hex) Function Name CONVERTER CONFIGURATION 00 00 Audio Codec Configuration 0 dB is related to the D/A full-scale output voltage (Please refer to Section 4.6.4. on page 72) bit[15:12] bit[11:8] A/D converter left amplifier gain = n*1.5-3 [dB] A/D converter right amplifier gain = n*1.5-3 [dB] 1111 +19.5 dB 1110 +18.0 dB ... ... 0011 +1.5 dB 0010 0.0 dB -1.5 dB 0001 - 3.0 dB 0000 Microphone amplifier gain = n*1.5+21 [dB] 1111 +43.5 dB 1110 +42.0 dB ... ... 0001 +22.5 dB 0000 +21.0 dB Input selection for left A/D converter channel 0 line-in 1 microphone Enable left A/D converter1) Enable right A/D converter1) Enable D/A converter1) CONV_CONF bit[7:4] bit[3] bit[2] bit[1] bit[0] 1) The generation of the internal DC reference voltage for the D/A converter is also controlled with this bit. In order to avoid click noise, the reference voltage at pin AGNDC should have reached a near ground potential before repowering the D/A converter after a short down phase. Alternatively at least one of the A/D converters (bits [2] or [1]) should remain set during short power-down phases of the D/A. Then the DC reference voltage generation for the D/A converter will not be interrupted. INPUT MODE SELECT 00 08 Input Mode Setting bit[15] Mono switch 0 stereo input mode 1 left channel is copied into the right channel Reserved, must be set to 0 Deemphasis select 0 deemphasis off 1 deemphasis 50 s 2 deemphasis 75 s ADC_IN_MODE bit[14:2] bit[1:0] Micronas 43 MAS 3587F Table 3-12: Codec control registers on I2C subaddress 6Chex Register Address (hex) Function ADVANCE INFORMATION Name OUTPUT MODE SELECT D/A Converter Source Mixer 00 06 00 07 MIX ADC scale MIX DSP scale bit[15:8] for example: 00hex 20hex 40hex 7Fhex off 50 % (-6 dB gain) 100 % (0 dB gain) 200 % (+6 dB gain) 00hex ... 7Fhex Linear scaling factor (hex) DAC_IN_ADC DAC_IN_DSP In the sum of both mixing inputs exceeds 100 %, clipping may occur in the successive audio processing. 00 0E D/A Converter Output Mode bit[15] Mono switch 0 stereo through 1 mono matrix applied Invert right channel 0 through 1 right channel is inverted Reserved, must be set to 0 DAC_OUT_MODE bit[14] bit[1:0] In order to achieve more output power a single loudspeaker can be connected as a bridge between pins OUTL and OUTR. In this mode bit[15] and bit[14] must be set. BASEBAND FEATURES 00 14 Bass bit[15:8] Bass range 60hex 58hex ... 08hex 00hex F8hex ... A8hex A0hex BASS +12 dB +11 dB +1 dB 0 dB -1 dB -11 dB -12 dB Higher resolution is possible, one LSB step results in a gain step of about 1/8 dB. With positive bass settings clipping of the output signal may occur. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. The settings require: max (bass, treble) + loudness + volume 0 dB bit[7:0] Not used, must be set to 0 44 Micronas ADVANCE INFORMATION MAS 3587F Table 3-12: Codec control registers on I2C subaddress 6Chex Register Address (hex) 00 15 Function Name Treble bit[15:8] Treble range 60hex +12 dB +11 dB 58hex ... 08hex +1 dB 0 dB 00hex -1 dB F8hex ... -11 dB A8hex -12 dB A0hex TREBLE Higher resolution is possible, one LSB step results in a gain step of about 1/8 dB. With positive treble settings, clipping of the output signal may occur. Therefore, it is not recommended to set treble to a value that, in conjunction with loudness and volume, would result in an overall positive gain. The settings require: max (bass, treble) + loudness + volume 0 dB bit[7:0] 00 1E Loudness bit[15:8] Loudness Gain 44hex +17 dB +16 dB 40hex ... +1 dB 04hex 0 dB 00hex Loudness Mode normal (constant volume at 1 kHz) 00hex Super Bass (constant volume at 2 kHz) 04hex Not used, must be set to 0 LDNESS bit[7:0] Higher resolution of Loudness Gain is possible: An LSB step results in a gain step of about 1/4 dB. Loudness increases the volume of low- and high-frequency signals, while keeping the amplitude of the 1-kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. The settings should be: max (bass, treble) + loudness + volume 0 dB The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz. Micronas 45 MAS 3587F Table 3-12: Codec control registers on I2C subaddress 6Chex Register Address (hex) Function ADVANCE INFORMATION Name Micronas Dynamic Bass (MDB) 00 22 MDB Effect Strength bit[15:8] 00hex 7Fhex MDB off (default) maximum MDB MDB_STR The MDB effect strength can be adjusted in 1dB steps. A value of 40hex will yield a medium MDB effect. 00 23 MDB Harmonics bit[15:8] 00hex 64hex 7Fhex no harmonics are added (default) 50% fundamentals + 50% harmonics 100% harmonics MDB_HAR The MDB exploits the psychoacoustic phenomenon of the `missing fundamental by creating harmonics of the frequencies below the center frequency of the bandpass filter (MDB_FC). This enables a loudspeaker to display frequencies that are below its cutoff frequency. The Variable MDB_HAR describes the ratio of the harmonics towards the original signal. 00 24 MDB Center Frequency bit[15:8] 2 3 ... 30 20 Hz 30 Hz 300 Hz MDB_FC The MDB Center Frequency defines the center frequency of the MDB bandpass filter (see Fig. 3-4 on page 49). The center frequency should approximately match the cutoff frequency of the loudspeakers. For high end loudspeakers, this frequency is around 50 Hz, for low end speakers around 90 Hz 00 21 MDB Shape bit[15:8] 5...30 corner frequency in 10-Hz steps (range: 50...300 Hz) MDB_SHAPE With a second lowpass filter the steepness of the falling slope of the MDB bandpass can be increased (see Fig. 3-4 on page 49). Choosing the corner frequency of this filter close to the center frequency of the bandpass filter (MDB_FC) results in a narrow MDB frequency range. The smaller this range, the harder the bass sounds. The recommended value is around 1.5 x MDB_FC MDB Switch bit[7:2] bit[1] 0 1 bit [0] reserved, must be set to zero MDB switch MDB off MDB on reserved, must be set to zero MDB_SWITCH 46 Micronas ADVANCE INFORMATION MAS 3587F Table 3-12: Codec control registers on I2C subaddress 6Chex Register Address (hex) VOLUME 00 10 Volume Control bit[15:8] Volume table with 1 dB step size 7Fhex +12 dB (maximum volume) +11 dB 7Ehex ... 74hex +1 dB 0 dB 73hex -1 dB 72hex ... -113 dB 02hex -114 dB 01hex mute (reset) 00hex Not used, must be set to 0 VOLUME Function Name bit[7:0] This main volume control is applied to the analog outputs only. It is split between a digital and an analog function. In order to avoid noise due to large changes of the setting, the actual setting is internally low-pass filtered. With large scale input signals, positive volume settings may lead to signal clipping. 00 11 Balance bit[15:8] Balance range left -127 dB, right 0 dB 7Fhex left -126 dB, right 0 dB 7Ehex ... left -1 dB, right 0 dB 01hex left 0 dB, right 0 dB 00hex FFhex left 0 dB, right -1 dB ... left 0 dB, right -127 dB 81hex left 0 dB, right -128 dB 80hex BALANCE Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. 00 12 Automatic Volume Correction (AVC) Loudspeaker Channel bit[15:12] 0hex 8hex bit[11:8] 8hex 4hex 2hex 1hex AVC off (and reset internal variables) AVC on 8 s decay time 4 s decay time 2 s decay time 20 ms decay time (intended for quick adaptation to the average volume level after track or source change) AVC Note: To reset the internal variables, the AVC should be switched off and then on again during any track or source change. For standard applications, the recommended decay time is 4 s. Micronas 47 MAS 3587F Table 3-13: Codec status registers on I2C subaddress 6Dhex Register Address (hex) Function ADVANCE INFORMATION Name INPUT QUASI-PEAK 00 0A A/D Converter Quasi-Peak Detector Readout Left bit[14:0] 0000 2000 4000 7FFF 00 0B positive 15-bit value, linear scale 0% 25% (-12 dBFS) 50% (-6 dBFS) 100% (0 dBFS) QPEAK_R QPEAK_L A/D Converter Quasi-Peak Detector Readout Right bit[14:0] 0000 2000 4000 7FFF positive 15-bit value, linear scale 0% 25% (-12 dBFS) 50% (-6 dBFS) 100% (0 dBFS) OUTPUT QUASI-PEAK 00 0C Audio Processing Input Quasi-Peak Detector Readout Left bit[14:0] 00 0D positive 15-bit value, linear scale DQPEAK_R DQPEAK_L Audio Processing Input Quasi-Peak Detector Readout Right bit[14:0] positive 15-bit value, linear scale 48 Micronas ADVANCE INFORMATION MAS 3587F 3.4.4. Basic MDB Configuration With the parameters described in Table 3-12, the Micronas Dynamic Bass system (MDB) can be customized to create different bass effects as well as to fit the MDB to various loudspeaker characteristics. The easiest way to find a good set of parameter is by selecting one of the settings below, listening to music with strong bass content and adjusting the MDB parameters: - MDB_STR: Increase/decrease the strength of the MDB effect - MDB_HAR: Increase/decrease the content of low frequency harmonics - MDB_FC: Shift the MDB effect to lower/higher frequencies - MDB_SHAPE: Widen/narrow MDB frequency range (which results in a softer/harder bass sound), turn on/off the MDB Amplitude (db) Signal Level Frequency MDB_FC MDB_SHAPE Fig. 3-4: Micronas Dynamic Bass (MDB): Bass boost in relation to input signal leve Table 3-14: Suggested MDB settings Function MDB off Low end headphones, medium effect MDB_STR (22hex) xxxxhex 5000hex MDB_HAR (23hex) xxxxhex 3000hex MDB_FC (24hex) xxxxhex 0600hex MDB_SHAPE (21hex) 0000hex 0902hex Micronas 49 MAS 3587F 4. Specifications 4.1. Outline Dimensions ADVANCE INFORMATION 15 x 0.5 = 7.5 0.1 0.145 0.055 48 49 12 0.2 33 15 x 0.5 = 7.5 0.1 D0025/3E 0.5 32 10 0.1 0.5 10 0.1 1.75 64 1 1.75 12 0.2 16 17 1.4 0.05 1.5 0.1 0.1 Fig. 4-1: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 g Dimensions in mm 4.2. Pin Connections and Short Descriptions NC LV X not connected, leave vacant If not used, leave vacant obligatory, pin must be connected as described in application information (see Fig. 4-30 on page 79) VDD connect to positive supply VSS connect to ground Pin No. PLQFP 64-pin 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name Type 0.22 0.05 Default Connection (if not used) X Short Description AGNDC MICIN MICBI INL INR TE XTI XTO POR VSS XVSS VDD IN IN IN IN IN IN OUT IN SUPPLY SUPPLY SUPPLY Analog reference voltage Input for internal microphone amplifier Bias for internal microphone Left A/D input Right A/D input Test enable Crystal oscillator (ext. clock) input Crystal oscillator output Power on reset, active low DSP supply ground Digital output supply ground DSP supply LV LV LV LV X X LV X X X X 50 Micronas ADVANCE INFORMATION MAS 3587F Pin No. PLQFP 64-pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name Type Default Connection (if not used) X X X VDD LV VSS VSS LV VDD VSS LV X X LV LV LV LV LV LV VDD VSS LV LV LV LV LV LV LV LV LV Short Description XVDD I2CVDD DVS VSENS1 DCSO1 DCSG1 DCSG2 DCSO2 VSENS2 DCEN CLKO I2CC I2CD SYNC VBAT PUP EOD PRTR PRTW PR PCS PI19 PI18 PI17 PI16 PI15 PI14 PI13 PI12 SOD SUPPLY SUPPLY IN IN/OUT SUPPLY SUPPLY SUPPLY SUPPLY IN/OUT IN OUT IN/OUT IN/OUT OUT IN OUT OUT OUT OUT IN IN IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT Digital output supply I2C supply I2C device address selector Sense input and power output of DC/DC 1 converter DC/DC 1 switch output DC/DC 1 switch ground DC/DC 2 switch ground DC/DC 2 switch output Sense input and power output of DC/DC 2converter DC/DC enable (both converters) Clock output I2C clock I2C data Sync output Battery voltage monitor input DC Converter Power-Up Signal PIO end of DMA, active low PIO ready to read, active low PIO ready to write, active low PIO DMA request, active high PIO chip select, active low PIO data bit 7 (MSB) PIO data bit 6 PIO data bit 5 PIO data bit 4 PIO data bit 3 PIO data bit 2 PIO data bit 1 PIO data bit 0 (LSB) Serial output data Micronas 51 MAS 3587F ADVANCE INFORMATION Pin No. PLQFP 64-pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name Type Default Connection (if not used) LV LV VSS VSS VSS LV VSS VSS VSS LV LV LV X X LV LV X X X X Short Description SOI SOC SID SII SIC SPDO SIBD SIBC SIBI SPDI2 SPDI1 SPDIR FILTL AVDD0 OUTL OUTR AVSS0 FILTR AVSS1 VREF PVDD AVDD1 OUT OUT IN IN IN OUT IN IN IN IN IN IN IN SUPPLY OUT OUT SUPPLY IN SUPPLY Serial output frame identification Serial output clock Serial input data, interface A Serial input frame identification, interface A Serial input clock, interface A S/PDIF output interface Serial input data, interface B Serial input clock, interface B Serial input frame identification, interface B Active differential S/PDIF input 2 Active differential S/PDIF input 1 Reference differential S/PDIF input 1 and 2 Feedback input for left amplifier Analog supply for output amplifiers Left analog output Right analog output Analog ground for output amplifiers Feedback for right output amplifier Analog ground Analog reference ground Internal power supply Analog Supply SUPPLY SUPPLY X X 52 Micronas ADVANCE INFORMATION MAS 3587F VSENS1/VSENS2 IN Sense input and power output of DC/DC converters. If the respective DC/DC converter is not used, this pin should be connected to a supply. DCEN IN Enable signal for both DC/DC converters. If none of the DC/DC converters is used, this pin must be connected to VSS. PUP OUT Power-up. This signal is set when the required voltages are available at both DC/DC converter output pins VSENS1 and VSENS2. The signal is cleared when both voltages have dropped below the reset level in the DCCF Register. VBAT Analog input for battery voltage supervision. IN 4.3. Pin Descriptions 4.3.1. Power Supply Pins The use of all power supply pins is mandatory to achieve correct function of the MAS 3587F. VDD, VSS Digital supply pins. XVDD, XVSS Supply for digital output pins. SUPPLY SUPPLY I2CVDD SUPPLY Supply for I2C interface circuitry. This net uses VSS or XVSS as the ground return line. PVDD SUPPLY Auxiliary pin for analog circuitry. This pin has to be connected via a 3-nF capacitor to AVDD1. Extra care should be taken to achieve a low inductance PCB line. AVDD0/AVSS0 SUPPLY Supply for analog output amplifier (output stage). AVDD1/AVSS1 SUPPLY Supply for internal analog circuits (A/D, D/A converters, clock, PLL, S/PDIF input). AVDD0/AVSS0 and AVDD1/AVSS1 should receive the same supply voltages. 4.3.4. Oscillator Pins and Clocking XTI IN XTO OUT The XTI pin is connected to the input of the internal crystal oscillator, the XTO pin to its output. Each pin should be directly connected to the crystal and to a ground-connected capacitor (see application diagram). CLKO The CLKO can drive an output clock line. OUT 4.3.2. Analog Reference Pins 4.3.5. Control Lines AGNDC Internal analog reference voltage. This pin serves as the internal ground connection for the analog circuitry. VREF Analog reference ground. All analog inputs and outputs should drive their return currents using separate traces to a ground starpoint close to this pin. Connect to AVSS1. This reference pin should be as noise free as possible. I2CC SCL I2CD SDA Standard I2C control lines. IN/OUT IN/OUT DVS IN I2C device address selector. Connect this pin either to VDD (I2C device address: 3E/3Fhex) or VSS (I2C device address: 3C/3Dhex) to select a proper I2C device address (see also Table 3-1 on page 17). 4.3.3. DC/DC Converters and Battery Voltage Supervision DCSG1/DCSG2 SUPPLY DC/DC converters switch ground. Connect using separate wide trace to negative pole of battery cell. Connect also to AVSS0/1 and VSS/XVSS. DCSO1/DCSO2 SUPPLY DC/DC converter switch connection. If the respective DC/DC converter is not used, this pin must be left vacant. 4.3.6. Parallel Interface Lines PI12..PI19 IN/OUT The PIO input pins PI12..PI19 are used as 8-bit I/O interface to a microcontroller in order to transfer compressed and uncompressed data. PI12 is the LSB, PI19 the MSB. Micronas 53 MAS 3587F 4.3.6.1. PIO Handshake Lines IN PCS The PIO chip select PCS must be set to `0' to activate the PIO in operation mode. PR IN Pin PR must be set to `1' when ready to send/receive data to/from MAS 3587F PIO pins. OUT PRTR Ready to read. This signal indicates that the MAS 3587F is able to receive data in PIO input mode. OUT PRTW Ready to write. This pin indicates that MAS 3587F has data available in PIO output mode. OUT EOD EOD indicates the end of an DMA cycle in the IC's PIO input/output mode. In 'serial' input mode it is used as Demand signal, that indicates that new input data are required. ADVANCE INFORMATION 4.3.10. S/PDIF Input Interface SPDI1 IN SPDI2 IN SPDIR IN SPDIF1 and SPDIF2 are alternative input pins for S/PDIF sources according to the IEC 958 consumer specification. A switch at D0:7f2 selects one of these pins at a time. The SPDIR pin is a common reference for both input lines (see Fig. 4-31 on page 80). 4.3.11. S/PDIF Output Interface SPDO OUT The SPDO pin provides an digital output with standard CMOS level that is compliant to the IEC 958 consumer specification. 4.3.12. Analog Input Interfaces The analog inputs are used in the standard MPEG encoding DSP firmware. They can also be selected as a source for the D/A converters (refer to audio codec register 00 07hex (see Table 3-12 on page 43)). MICIN IN MICBI IN The MICIN input may be directly used as electret microphone input, which should be connected as described in application information. The MICBI signal provides the supply voltage for these microphones. INL IN INR IN INL and INR are analog line-in input lines. They are connected to the embedded stereo A/D converter of the MAS 3587F. The sources should be AC coupled. The reference ground for these analog input pins is the VREF pin. 4.3.7. Serial Input Interface (SDI) SID DATA IN SII WORD STROBE IN SIC CLOCK IN I2S compatible serial interface A for digital audio data. This interface can be used for audio input in the encoder. 4.3.8. Serial Input Interface B (SDIB) SIBD DATA IN SIBI WORD STROBE IN SIBC CLOCK IN The serial interface B is used as bitstream input interface. The SIBI line must be connected to VSS in the serial decoder application. 4.3.13. Analog Output Interfaces 4.3.9. Serial Output Interface (SDO) SOD DATA OUT SOI WORD STROBE OUT SOC CLOCK IN/OUT Data, Frame Indication, and Clock line of the serial output interface. The SDO is reconfigurable and can be adapted to several I2S compliant modes. OUTL OUT OUTR OUT OUTL and OUTR are left and right analog outputs, that may be directly connected to built-in 16 loudspeakers via 22 series resistance to the headphones as described in the application information (see Fig. 4-30 on page 79). FILTL IN FILTR IN Connection to input terminal of output amplifier.Can be used to connect a capacitance from OUTL respectively OUTR to FILTL respectively FILTR in parallel to feedback resistor and thus implement a low pass filter to reduce the out-of-band noise of the DAC. 54 Micronas ADVANCE INFORMATION MAS 3587F 4.3.14. Miscellaneous SYNC OUT The SYNC signal indicates the detection of a frame start in the input data of MAS 3587F. Usually this signal generates an interrupt in the controller. IN POR The Power-On Reset pin is used to reset the whole MAS 3587F, except for the DC/DC converter circuitry. POR is an active-low signal. TE IN The TE pin is for production test only and must be connected with VSS in all applications. 4.4. Pin Configurations PI12 SOD SOI SOC SID SII SIC SPDO PI13 PI14 PI15 PI16 PI17 PI18 PI19 PCS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SIBD SIBC SIBI SPDI2 SPDI1 SPDIR FILTL AVDD0 OUTL OUTR AVSS0 FILTR AVSS1 VREF PVDD AVDD1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 AGNDC MICIN MICBI INL INR TE XTI XTO 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSENS1 DVS I2CVDD XVDD VDD XVSS VSS POR 32 31 30 29 28 27 26 PR PRTW PRTR EOD PUP VBAT SYNC I2CD I2CC CLKO DCEN VSENS2 DCSO2 DCSG2 DCSG1 DCSO1 MAS 3587F 25 24 23 22 21 20 19 18 17 Fig. 4-2: PLQFP64 package (Top view) Micronas 55 MAS 3587F 4.5. Internal Pin Circuits ADVANCE INFORMATION VDD TTLIN N Fig. 4-3: Input pins PCS, PR VSS Fig. 4-8: Input/output pins I2CC, I2CD VSENS Fig. 4-4: Input pin TE, DVS, POR P DCSO N DCSG Fig. 4-9: Input/output pins DCSO1/2, DCSG1/2, VSENS1/2 Fig. 4-5: Input pin DCEN XVDD XVDD P N N XVSS Fig. 4-6: Input/output pins SOC, SOI, SOD, PI12...PI19, SPDO P XVSS Fig. 4-10: Output pins PRTW, EOD, PRTR, CLKO, SYNC, PUP AVDD XVDD P XTI P N N Enable N AVSS Fig. 4-11: Clock oscillator XTI, XTO P P XTO N XVSS Fig. 4-7: Input pins SI(B)C, SI(B)I, SI(B)D 56 Micronas ADVANCE INFORMATION MAS 3587F MICIN INL INR XVDD - + A D SPDI1, SPDI2 SPDIR - + XVDD Bias AGNDC Fig. 4-12: Analog input pins MICIN, INL, INR Fig. 4-16: S/PDIF inputs AGNDC + - MICBI VBAT VREF Fig. 4-13: Microphone bias pin (MICBI) + - VSS = VSS programmable FILTL(R) Fig. 4-17: Battery voltage monitor VBAT D A I - + OUTL(R) AGNDC Fig. 4-14: Analog outputs OUTL(R) and connections for filter capacitors FILTL(R) + - AGNDC 1.25 V VREF Fig. 4-15: Analog ground generation with pin to connect external capacitor Micronas 57 MAS 3587F 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA TS PTOT Parameter Ambient operating temperature Storage Temperature Power dissipation VDD, XVDD, AVDD0/1, I2CVDD AVDD0/1 VDD, XVDD, I2CVDD I2CC, I2CD Pin Name Min. ADVANCE INFORMATION Max. 85 125 650 Unit C C mW -40 -40 VSUPA VSUP VII2C VIdig IIdig VIana IIana IOaudio IOdig IOdcdc1 IOdcdc2 1) 2) 3) Analog supply voltages1) Digital supply voltage Input voltage, I2C-Pins Input voltage, all digital inputs Input current, all digital inputs Input voltage, all analog inputs Input current, all analog inputs Output current, audio output2) Output current, all digital outputs3) Output current DCDC converter 1 Output current DCDC converter 2 -0.3 -0.3 -0.3 -0.3 -20 -0.3 -5 6 6 6 VSUP +0.3 +20 VSUP + 0.3 +5 0.2 +50 1.5 1.5 V V V V mA V mA A mA A A OUTL/R -0.2 -50 DCSO1 DCSO2 Both AVDD0 and AVDD1 have to be connected together! These pins are not short-circuit proof! Total chip power dissipation must not exceed absolute maximum rating Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 58 Micronas ADVANCE INFORMATION MAS 3587F 4.6.2. Recommended Operating Conditions Symbol Parameter Pin Name Min. Typ. Max. Unit Temperature Range 1 and Supply Voltages TA1 VSUPD1 VSUPD2 Ambient temperature range 1 Digital supply voltage (MPEG decoder) Digital supply voltage (MPEG 1 encoder) Digital supply voltage (MPEG 2 encoder) VSUPI2C VSUPA I2C bus supply voltage Analog audio supply voltage Analog audio supply voltage in relation to the digital supply voltage VSUPx 1) -40 VDD, XVDD 2.2 2.5 3.5 2.7 I2CVDD AVDD0/1 VSUPDn1) at VDD 2.2 0.62 2.7 85 3.9 3.9 3.9 3.9 3.9 1.6 C V V V VSUPD PIN supply voltage in relation to digital supply voltage XVDD 0.62 1.6 VSUPD n = 1,2 Table 4-1: Reference Frequency Generation and Crystal Recommendation Symbol Parameter Pin Name Min. Typ. Max. Unit External Clock Input Recommendations fCLK VCLKI Clock frequency Clockamplitude of external clock fed into XTI at VAVDD = 2.2 V Clockamplitude of external clock fed into XTI at VAVDD = 2.7 V Clockamplitude of external clock fed into XTI at VAVDD = 3.3 V Clockamplitude of external clock fed into XTO at VAVDD = 2.2 V Clockamplitude of external clock fed into XTO at VAVDD = 2.7 V Clockamplitude of external clock fed into XTO at VAVDD = 3.3 V Duty cycle XTI, XTO XTO XTI, XTO XTI 13.00 0.7 0.55 0.45 1.25 0.75 0.55 45 50 18.432 20.00 1.05 1.5 1.75 2.2 2.7 3.3 55 % MHz VPP Micronas 59 MAS 3587F Table 4-1: Reference Frequency Generation and Crystal Recommendation Symbol Parameter Pin Name Min. ADVANCE INFORMATION Typ. Max. Unit Crystal Recommendations fP Load resonance frequency at CI = 20 pF Accuracy of frequency adjustment Frequency variation vs. temperature Equivalent series resistance Shunt (parallel) capacitance XTI, XTO 18.432 MHz 50 50 12 3 30 5 ppm ppm f/fS f/fS REQ C0 -50 -50 pF Table 4-2: Input Levels Symbol IIL IIH IIL IIH IILD IIHD Parameter Input low voltage at VDD = 2.5...3.9 V Input high voltage at VDD = 2.5...3.9 V Input low voltage at VDD = 2.5...3.9 V Input high voltage at VDD = 2.5...3.9 V Input low voltage Input high voltage PI, SI(B)I, SI(B)C, SI(B)D, PR, PCS, TE, DVS POR, DCEN 0.9 0.3 VSUP -0.5 Pin Name I2CC, I2CD 1.4 0.2 Min. Typ. Max. 0.3 Unit V V V V V V 60 Micronas ADVANCE INFORMATION MAS 3587F Table 4-3: Analog Input and Output Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit Analog Reference CAGNDC1 CAGNDC2 CPVDD Analog filter capacitor Ceramic capacitor in parallel Capacitor for analog circuitry PVDD 3 AGNDC 1.0 3.3 10 F nF nF Analog Audio Inputs CinAD CinMI CLMICBI DC-decoupling capacitor at A/Dconverter inputs DC-decoupling capacitor at microphone-input Minimum-Capacitance at microphone bias INL/R MICIN MICBI 3.3 390 390 nF nF nF Analog Audio Filter Outputs CFILT Filter capacitor for headphone amplifier high-Q type, NP0 or C0G material FILTL/R OUTL/R -20 % 470 +20 % pF Analog Audio Output ZAOL_HP Analog output load with stereo headphones OUTL/R 16 100 DC/DC-Converter External Circuitry (please refer to application example) C1 VTH L VSENS blocking (<100 m ESR) Schottky diode threshold voltage Ferrite ring core coil inductance VSENS1/2 DCSO1/2 VSENS1/2 DCSO1/2 22 330 0.35 F V H pF S/PDIF Interface Analog Input CSPI S/PDIF coupling capacitor SPDI1/2 SPDIR 100 nF Micronas 61 MAS 3587F 4.6.3. Digital Characteristics ADVANCE INFORMATION at TA = TA2, VSUPDn, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Digital Supply Voltage ISUPD1 Current consumption (MPEG decoding) VDD, XVDD, I2CVDD 39 20 11 ISUPD2 Current consumption (MPEG encoding) 145 70 ISTANDBY Total current at stand-by 10 A mA 2.5 V, sampling frequency 32 kHz 2.5 V, sampling frequency 24 kHz 2.5 V, sampling frequency 12 kHz 3.5 V, sampling frequency 32 kHz 2.7 V, sampling frequency 24 kHz DSP off, Codec off, DC /DC off, A/D and D/AC off, no I2C access Digital Outputs and Inputs ODigL ODigH Output low voltage Output low voltage PI, SOI, SOC, SOD, EOD, PRTR, PRTW, CLKO, SYNC, PUP, SPDO all digital Inputs -1 0.3 VSUPD -0.3 V V Iload = 2 mA Iload = -2 mA ZDigI IDLeak Input impedance Digital input leakage current 7 1 pF A 0 V < Vpin < VSUPD 62 Micronas ADVANCE INFORMATION MAS 3587F 4.6.3.1. I2C Characteristics at TA=25C, VSUPI2C = 2.5...3.6 V Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions I2C Input Specifications fI2C tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2COL II2COH tI2COL1 tI2COL2 VI2CIL VI2CIH tW Upper limit I2C bus frequency operation I2C START condition setup time I2C STOP condition setup time I2C clock low pulse time I C clock high pulse time I2C data setup time before rising edge of clock I2C data hold time after falling edge of clock I2C output low voltage I2C output high leakage current I2C data output hold time after falling edge of clock I2C data output setup time before rising edge of clock I2C input low voltage I2C input high voltage Wait time 2 I2CC I2CC, I2CD I2CC, I2CD I2CC I2CC I2CC I2CC I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC; I2CD I2CC, I2CD I2CC, I2CD 400 300 300 1250 1250 80 80 0.4 1 20 250 0.3 0.6 0 0.5 4 kHz ns ns ns ns ns ns V A ns ns VSUPI2C VSUPI2C ms fI2C = 400 kHz Iload = 3 mA 1/fI2C tI2C4 H L tI2C3 I2CC tI2C1 tI2C5 tI2C6 tI2C2 H L I2CD as input tI2COL2 tIC2OL1 H L I2CD as output Fig. 4-18: I2C timing diagram Micronas 63 MAS 3587F 4.6.3.2. Serial (I2S) Input Interface Characteristics (SDI, SDIB) ADVANCE INFORMATION at TA = TA2, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C Symbol tSICLK Parameter I2S clock input clock period Pin Name SI(B)C Min. Typ. 325 Max. Unit ns Test Conditions fS = 48 kHz Stereo, 32 bits per sample (for demand mode see Table 4-4) tSIDS I2S data setup time before rising edge of clock (for continuous data stream: falling edge) I2S data hold time I2S ident setup time before rising edge of clock (for continuous data stream: falling edge) I2S ident hold time Burst wait time SI(B)C, SI(B)D 50 ns tSIDH tSIIS SI(B)D SI(B)C, SI(B)I 50 50 ns ns tSIIH tbw SI(B)I SI(B)C, SI(B)D 50 480 ns Table 4-4: Maximum demand clock frequency fSample (kHz) 48, 32 44.1 24, 16 22.05 12, 8 11.025 fC (MHz) 6.144 5.6448 3.072 2.8224 1.536 1.4112 min. tSICLK 162 177 325 354 651 708 64 Micronas ADVANCE INFORMATION MAS 3587F TSICLK H SI(B)C L H SI(B)I L SI(B)D H L TSIDS TSIDH Fig. 4-19: Continuous data stream at serial input A or B. In this mode, the word strobe SI(B)I is not used and the data are read at the falling edge of the clock (bit 2 in D0:7f1 is set). TSICLK SI(B)C H L SI(B)I H L TSIIS SI(B)D H L TSIIH TSIDS Fig. 4-20: Serial input of I2S signal TSIDH Micronas 65 MAS 3587F 4.6.3.3. Serial Output Interface Characteristics (SDO) ADVANCE INFORMATION at TA = TA2, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C Symbol tSOCLK tSOISS tSOODC Parameter I2S clock output frequency I2S word strobe delay time after falling edge of clock I2S data delay time after falling edge of clock Pin Name SOC SOC, SOI SOC, SOD 0 0 Min. Typ. 325 Max. Unit ns ns ns Test Conditions fS = 48 kHz Stereo 32 bits per sample TSOCLK H SOC L SOI H L TSOISS SOD H L TSOISS TSOODC Fig. 4-21: Serial output interface timing. 66 Micronas ADVANCE INFORMATION MAS 3587F Vh SOC Vl Vh SOD Vl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 76543210 SOI Vh Vl left 16-bit audio sample right 16-bit audio sample Fig. 4-22: Sample timing of the SDO interface in 16 bit/sample mode. D0:7f1 settings are: Bit 14 = 0 (SOC not inverted), bit 11 = 1 (SOI delay), bit 5 = 0 (word strobe not inverted), bit 4 = 1 (16 bits/sample). SOC Vh Vl ... ... Vh SOD Vl Vh 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 SOI Vl left 32-bit audio sample right 32-bit audio sample Fig. 4-23: Sample timing of the SDO interface in 32 bit/sample mode. D0:7f1 settings are: Bit 14 = 0 (SOC not inverted), bit 11 = 0 (no SOI delay), bit 5 = 1 (word strobe inverted), bit 4 = 0 (32 bits/sample). Micronas 67 MAS 3587F 4.6.3.4. S/PDIF Input Characteristics ADVANCE INFORMATION at TA = TA2, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C. Symbol VS fs1 fs2 fs3 tP tR tF Parameter Signal amplitude Bi-phase frequency Bi-phase frequency Bi-phase frequency Bi-phase period Rise time Fall time Duty cycle tH1,L1 Pin Name SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI SPDI 0 0 40 81 50 Min. 200 Typ. 500 2.048 2.822 3.072 326 65 65 60 163 Max. 1000 Unit mVpp MHz MHz MHz ns ns ns % ns 1000 ppm, fs = 48 kHz 1000 ppm, fs = 44.1 kHz 1000 ppm, fs = 32 kHz at fs = 48 kHz, (highest sampling rate) at fs = 48 kHz, (highest sampling rate) at fs = 48 kHz, (highest sampling rate) at bit value=1 and fs = 48 kHz minimum/maximum pulse duration with a level above 90 % or below 10 % and at fs = 48 kHz minimum/maximum pulse duration with a level above 90 % or below 10 % and at fs = 48 kHz Test Conditions tH0,L0 SPDI 163 244 ns tR tH1 Bit value = 1 tH0 Bit value = 0 tP tF tL1 tL0 Fig. 4-24: Timing of the S/PDIF input 68 Micronas ADVANCE INFORMATION MAS 3587F 4.6.3.5. S/PDIF Output Characteristics at TA = TA2, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C. Symbol fs1 fs2 fs3 tP tR tF Parameter Bi-phase frequency Bi-phase frequency Bi-phase frequency Bi-phase period Rise time Fall time Duty cycle tH1,L1 Pin Name SPDO SPDO SPDO SPDO SPDO SPDO SPDO SPDO 0 0 50 163 Min. Typ. 3.072 2.822 2.048 326 2 2 Max. Unit MHz MHz MHz ns ns ns % ns minimum/maximum pulse duration with a level above 90 % or below 10 % and at fs = 48 kHz minimum/maximum pulse duration with a level above 90 % or below 10 % and at fs = 48 kHz Test Conditions fs = 48 kHz fs = 44.1 kHz fs = 32 kHz at fs = 48 kHz, (highest sampling rate) Cload = 10 pF Cload = 10 pF tH0,L0 SPDO 326 ns VS Signal amplitude SPDO VSUPD tR tH1 Bit value = 1 tH0 Bit value = 0 tP tF tL1 tL0 Fig. 4-25: Timing of the S/PDIF output Micronas 69 MAS 3587F 4.6.3.6. PIO as Parallel Input Interface: DMA Mode In decoding mode, the data transfer can be started after the EOD pin of the MAS 3587F is set to "high". After verifying this, the controller signalizes the sending of data by activating the PR line. The MAS 3587F responds by setting the RTR line to the "low" level. The MAS 3587F reads the data PI[19:12] and sets RTR to low after rising edge of PR. After RTR is set to high, the mC sets PR to low. The next data word write operation will be initialized again by setting the PR line via the controller. Please refer to Figure 4-26 for the exact timing The procedure above will be repeated until the MAS 3587F sets the EOD signal to "0" which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to "0", wait until EOD rises again and then repeat the procedure to send the next block of data. The DMA buffer is 15 bytes long. The buffer size is subject to change in the next version. ADVANCE INFORMATION Symbol tst tr tpd tset th trtrq tpr trpr teod teodq Pin Name PR, EOD PR, RTR PR, PI[19:12] PI[19:12] PI[19:12] RTR PR PR, RTR PR, EOD EOD Min. 0.010 40 120 160 160 200 480 160 40 2.5 Max. 2000 160 480 Unit s ns ns ns ns 30000 ns ns ns 160 500 ns s . tst tr tpd trtrq trpr teod teodq high EOD tpr PR low high low high RTR tset PI[19:12] Byte 1 Byte 15 MAS 3509F latches the PIO DATA th high low low Fig. 4-26: Handshake protocol for writing MPEG data to the PIO-DMA 70 Micronas ADVANCE INFORMATION MAS 3587F Table 4-5: PIO output mode timing Symbol t0 t1 t2 t3 t4 t5 teod teodq Pin EOD, PR PR, PI PI, RTW RTW, PR PR, RTW RTW, PR Min. 0.010 110 18 18 90 35 tbd 2.5 tbd 260 Max. 2000 310 55 Unit 4.6.3.7. PIO as Parallel Output Interface: DMA Mode In encoding mode, the MAS 3587F signals available data by setting the EOD pin to "high". After verifying this, the controller signalizes its capability to receive one byte of data by activating the PR line. The MAS 3587F responds by setting the RTW line to the "low" level when the actual byte is set on the data lines PI[19:12]. After PR is set to "low" level, the RTW line is set to "high" again. The next data word write operation will be initialized again by setting the PR line via the controller. Please refer to Fig. 4-27 on page 71 for the exact timing. The procedure above will be repeated until the MAS 3587F sets the EOD signal to "0" which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to "0", wait until EOD rises again and then repeat the procedure to receive the next block of data. The DMA buffer is 15 bytes long. The buffer size is subject to change in the next version. In order to transfer the worst case data rate of 192 kbit/s, the controller must react sufficiently fast. The mean response times (t0, t3, t5) must be faster than 10 ms. Due to internal buffering in the MAS 3587F, this time can be expanded up to 4.8 ms once within each frame (see Table 2-2 on page 15) in any case. s ns ns ns ns ns ns ns t0 t1 t2 t3 t4 t5 teod teodq high EOD low high PR low high RTW low high PI[19:12] Byte 1 Byte 15 low Fig. 4-27: Handshake protocol for reading MPEG data from the PIO-DMA Micronas 71 MAS 3587F 4.6.4. Analog Characteristics at TA = TA2, VSUPD = 2.5...3.6 V, VSUPA = 2.2 ... 3.6 V, fCrystal = 13...20 MHz, typical values at TA = 25 C and fCRYSTAL = 18.432 MHz Symbol Parameter Pin Name Min. Typ. Max. Unit ADVANCE INFORMATION Test Conditions Analog Supply IAVDD IQOSC Current consumption analog audio Current consumption crystal oscillator AVDD0/1 AVDD0/1 5 200 mA A VSUPA = 2.2 V, Mute Codec = off DSP = off DC/DC = on Codec = off DSP = off DC/DC = off ISTANDBY 10 Crystal Oscillator VDCCLK VACLK CIN ROUT DC voltage at oscillator pins Clock amplitude Input capacitance Output resistance XTO XTI, XTO 0.5 3 220 125 94 Analog Audio VAI Analog line input clipping level (at minimum analog input gain,i.e. -3 dB) INL/R 2.2 2.6 3.2 VMI Microphone input clipping level (at minimum analog input gain, i.e. +21 dB) MICIN 141 167 282 mVpp Vpp VSUPA >2.2 V >2.4 V >3.0 V VSUPA >2.0 V >2.4 V >3.0 V Bits 15, 14 in Reg. 6Ahex 00 01 10 Bits 15,14 in Reg. 6Ahex 00 01 10 0.5 VSUPA -0.5 VSUPA VPP pF VSUPA = 2.2 V VSUPA = 2.7 V VSUPA = 3.3 V if crystal is used 72 Micronas ADVANCE INFORMATION MAS 3587F Symbol VAO1 Parameter Analog Output Voltage AC Pin Name OUTL/R Min. Typ. Max. Unit Test Conditions RL1 k Input=0 dBFS digital VSUPA Bits 15, 14 in Reg 6Ahex 00 01 10 00 01 10 at 0 dB output gain 1.56 1.84 2.27 Vpp >2.2 V >2.4 V >3.0 V at +3 dB output gain 2.20 2.60 3.20 Vpp >2.2 V >2.6 V >3.2 V dVAO1 Deviation of DC-Level at Analog Output for AGNDCVoltage Analog Output Voltage AC OUTL/R -20 20 mV VAO2 OUTL/R RLis 16 Headphone and 22 seriesresistor Input=0 dBFS digital (see Fig. 4-31 on page 80) VSUPA Bits 15, 14 in Reg 6Ahex 00 01 10 00 01 10 at 0 dB output gain 1.56 1.84 2.27 Vpp >2.2 V >2.4 V >3.0 V at +3 dB output gain 2.00 2.40 3.00 Vpp >2.2 V >2.6 V >3.2 V RinAI Analog line input resistance INL/R 97 20 67 k at minimum analog input gain, i.e. -3 dB at maximum analog input gain, i.e. +19.5 dB not selected RinMI Microphone input resistance MICIN 94 8 94 k at minimum analog input gain, i.e. -21 dB at maximum analog input gain, i.e. +43.5 dB not selected RinAO SNRAI Analog output resistance Signal-to-noise ratio of line input OUTL/R INL/R 74 6 dB(A) analog gain=+3 dB, Input=0 dBFS digital BW = 20 Hz...20 kHz, analog gain=0 dB, input 1 kHz at VAI-20 dB Micronas 73 MAS 3587F ADVANCE INFORMATION Symbol SNRMI Parameter Signal-to-noise ratio of microphone input Total harmonic distortion of analog inputs Pin Name MICIN Min. Typ. 73 Max. Unit dB(A) Test Conditions BW = 20 Hz...20 kHz, analog gain=+21 dB, input 1 kHz at VMI-20 dB BW = 20 Hz...20 kHz, analog gain = 0 dB, resp. 24 dB, input 1 kHz at -3 dBFS=VAI-6 dB resp. VMI-6 dB f = 1 kHz, sine wave, analog gain = 0 dB, input = -3 dBFS 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms THDAI INL/R MICIN 0,01 0.02 % XTALKAI Crosstalk attenuation left/right channel (analog inputs) INL/R MICIN 80 dB PSRRAI Power supply rejection ratio for analog audio inputs AVDD0/1, INL/R MICIN 45 20 dB dB Audio Output SNRAO Signal-to-noise ratio of analog output OUTL/R 94 dB(A) RL16 BW = 20 Hz...20 kHz, analog gain = 0 dB input = -20 dBFS THDAO Total harmonic distortion (headphone) for RL16 plus 22 series resistor (see Fig. 4-31 on page 80) for RL1k OUTL/R 0.03 0.05 % 0.003 OUTL/R -113 0.01 % dBV A-weighted BW=20 Hz...22kHz , no digital input signal, analog gain=mute LevMuteAO Mute level XTALKAO Crosstalk attenuation left/right channel (headphone) OUTLR 80 dB f=1 kHz, sine wave, OUTL/R: RL16 (see Fig. 4-31 on page 80) analog gain=0 dB input=-3 dBFS 1 kHz sine at 100 mVrms 100 kHz sine at 100mVrms RL >> 10 M, referred to VREF VSUPA Bits 15, 14 in Reg. 6Ahex 00 01 10 PSRRAO Power supply rejection ratio for analog audio outputs AVDD0/1 OUTL/R 70 35 dB dB V VAGNDC Analog Reference Voltage AGNDC 1.1 1.3 1.6 >2.2 V >2.4 V >3.0 V 74 Micronas ADVANCE INFORMATION MAS 3587F Symbol VMICBI Parameter Bias voltage for microphone Pin Name MICBI Min. Typ. Max. Unit Test Conditions VSUPA Bits 15, 14 in Reg. 6Ahex 00 01 10 1.8 2.13 2.62 RMICBI IMAX Source resistance Maximum current microphone bias MICBI MICBI 300 180 A >2.2 V >2.4 V >3.0 V VSUPA >2.2 V Bits 15, 14 in Reg. 6Ahex 00 Micronas 75 MAS 3587F 4.6.5. DC/DC Converter Characteristics ADVANCE INFORMATION at TA = TA2, Vin = 1.2 V (unless otherwise noted), Voutn = 3.0 V, fclk = 18.432 MHz, fsw = 384 kHz, Typ. values for TA = 25 C Symbol VIN VIN Parameter Minimum start-up input voltage Minimum operating input voltage DC1* DC2* DC1* DC2* VOUT Programmable output voltage range Output voltage tolerance Output current 1 battery cell Output current 2 battery cells Line regulation Load regulation DC1 DC2 hmax fswitch fstartup IsupPFM1 IsupPFM2 IsupPWM1 IsupPWM2 Ilnmax Ilptoff ILEAK 1) 2) Pin Name * Min. Typ. 0.9 Max. Unit V Test Conditions ILOAD 1 mA, DCCF = 5050hex (reset) 0.7 0.8 1.1 1.2 VSENSN 2.0 3.5 V V V ILOAD = 50 mA, DCCF = 5050hex (reset) ILOAD = 200 mA, DCCF = 5050hex (reset) Voltage settings in DCCF register (I2C subaddress 76hex) ILOAD = 20 mA TA = 25 C VIN = 0.9...1.5 V, 330 F VIN = 1.8...3.0 V, 330 F VOTOL ILOAD1 ILOAD2 dVOUT/ dVIN/VOUT dVOUT/ VOUT VSENSN VSENSN 2.88 3.12 200 600 V mA mA %/V VSENSN 0.8 VSENS1 VSENS2 - DCSOn DCSOn VSENS1 VSENS2 297 -1.7 -1.8 95 384 250 75 135 265 325 1 70 0.1 576 % ILOAD = 20...200 mA, Maximum efficiency Switching frequency Switching frequency during start-up Supply current in PFM mode % kHz kHz A VIN = 2.4 V, VOUT = 3.5 V (see Section 2.9.2. on page 11) VSENSn < 1.9 V 1) Supply current in PWM mode VSENS1 VSENS2 A VSENSn 1) 2) NMOS switch current limit (low side switch) PMOS switch turnoff current (rectifier switch) leakage current DCSOn, DCSGn DCSOn, VSENSn DCSOn, DCSGn A mA A Tj = 25 C, converter off, ILOAD = 0 A Current into VSENSn. VIN > VOUT+V; (V0.4 V); no DC/DC-Converter regulation switching action present Add. current of oscillator at PIN AVDD0/1, (see Section 4.6.4. on page 72) 76 Micronas ADVANCE INFORMATION MAS 3587F 4.6.6. Typical Performance Characteristics Efficiency vs. Load Current DCDC1 (VOUT = 3.5 V) 100 3.0 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 3.5 V) 3.0 V 80 Efficiency (%) 1.8 V Efficiency (%) 80 1.8 V 60 VIN: 3.0 V 2.4 V 1.8 V PFM PWM 60 VIN: 3.0 V 2.4 V 1.8 V PFM PWM 40 40 20 20 0 10-4 10-3 10-2 10-1 1 0 10-4 10-3 10-2 10-1 1 Load Current (A) Load Current (A) Efficiency vs. Load Current DCDC1 (VOUT = 3.0 V) 100 2.4 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 3.0 V) 2.4 V 80 Efficiency (%) Efficiency (%) 80 60 VIN: 2.4 V 1.5 V 1.2 V 0.9 V 0.9 V 60 VIN: 2.4 V 1.5 V 1.2 V 0.9 V 0.9 V 40 40 20 PFM PWM 20 PFM PWM 10-3 10-2 10-1 0 10-4 10-3 10-2 10-1 1 0 10-4 1 Load Current (A) Fig. 4-28: Efficiency vs. Load Current Load Current (A) Micronas 77 MAS 3587F ADVANCE INFORMATION Efficiency vs. Load Current DCDC1 (VOUT = 2.2 V) 100 1.5 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 2.2 V) 1.5 V 80 Efficiency (%) Efficiency (%) 80 60 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 60 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 40 40 20 PFM PWM 20 PFM PWM 0 10-4 10 -3 10 -2 10 -1 1 0 10-4 10-3 10-2 10-1 1 Load Current (A) Load Current (A) Maximum Load Current vs. Input Voltage 0.8 DCDC1 Vout: 2.2 V 3.0 V 3.5 V PFM PWM 0.8 Maximum Load Current vs. Input Voltage DCDC2 Maximum Load Current (A) Vout: 2.2 V 3.0 V 3.5 V PFM 0.4 PWM Maximum Load Current (A) 0.6 0.6 0.4 0.2 0.2 0 0.0 1.0 2.0 3.0 Input Voltage (V) Fig. 4-29: Maximum Load Current vs. Input Voltage Note: Efficiency is measured as VSENSn x ILOAD / (Vin x Iin). IAVDD is not included (Oscillator current) 0 0.0 1.0 2.0 3.0 Input Voltage (V) 78 Micronas Micronas 79 - MMC/SDI-Card or SMC/CF2+ used as storage media - Dashed lines show optional (external) devices 4.7. Typical Application in a Portable Player ADVANCE INFORMATION Fig. 4-30: Application circuit of the MAS 3587F. For connections of the DC/DC converters, please refer to Fig. 4-31. VDC1 VDC1 Serial memory device e.g. SD-Card I2S-I/O Parallel memory device e.g. SmartMediaCard, Hard Disk DigiAmp IEC 958 MPEG 2 D 3 3 MPEG 8 D Reference clock VDC1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOD SPDO SIC SII SID SOC SOI PI12 PI13 PI14 PI15 PI16 PI17 PI18 PI19 PCSQ D 10k 75 CD/DVD-player IEC 958 75 100n 100n 470p 100n SIBD SIBC SIBI SPDI2 SPDI1 SPDIR FILTL AVDD0 OUTL 220u L Headphone > 16 R 1.5k 100 1.5k 6.8n 22 100 6.8n 22u 3n A 10n 470p OUTR AVSS0 FILTR AVSS1 VREF PVDD AVDD1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 I2CVDD VSENS1 MICIN AGNDC 63 64 MICBI PORQ XVDD XVSS VSS XTI XTO VDD DVS INL INR TE 32 31 30 29 28 27 26 PR PRTWQ PRTRQ EODQ PUP VBAT SYNC I2CD I2CC CLKO DCEN VSENS2 DCSO2 DCSG2 DCSG1 DCSO1 See figure caption Place all cermic capacitors as close as possible to IC pins VDC1 470p capacitorss should be high-Q (NP0 or C0G) 18p D 390 n 390n A 18.432 MHz 3.6...5.6 k 3.3 n MIC 390p separate trace Tape recorder FM radio A Place VDD / XVDD -filter capacitors above ground plane 390n 390p 10k VDC2 VDC1 4u7 D A 18p 1.5u 1.5u Option for I2C-address connect to VSS or I2CVDD A D 3u3 10n 220p 1n 1n VDC2 4k7 VDC1 4k7 5 PIO-control 220u 22 MAS 3587F 25 24 23 22 21 20 19 18 17 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Star point ground connection very close to pins DCSG1 and DCSG2 MAS 3587F MAS 3587F 4.8. Recommended DC/DC Converter Application Circuit Configuration 1 (see Fig. 2-8 on page 13) VBAT DCSO1 ADVANCE INFORMATION L1 = 22 H D1, Schottky AVDD0/1 VSENS1 VDC1 e.g. 2.7 V C3 = 330 F + VIN (Input Voltage) (0.9..1.5 V) C1 = 330 F (low ESR) DCSG1 + MAS 3587F VSS, XVSS DCEN DCSO2 D Power-On Push Button L2 = 22 H D2, Schottky VSENS2 VDC2 e.g. 2.5 V/3.5 V + Star Point Ground Connection very close to Pins DCSG1 and DCSG2 A D C2 = 330 F (low ESR) DCSG2 VREF AVSS0/1 A Fig. 4-31: External circuitry for the DC/DC converters 80 Micronas ADVANCE INFORMATION MAS 3587F Micronas 81 MAS 3587F 5. Data Sheet History 1. Advance Information: "MAS 3587F MPEG Layer 3 Audio Encoder/Decoder", March 2, 2001, 6251-542-1AI. First release of the advance information. ADVANCE INFORMATION Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-542-1AI All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 82 Micronas This datasheet has been download from: www..com Datasheets for electronics components. |
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